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/xen/docs/misc/
A Dxl-psr.pandoc10 the usage of cache (currently only L3 cache supported) by applications running
30 After that, cache usage for the domain can be shown by:
32 `xl psr-cmt-show cache-occupancy <domid>`
73 partition cache allocation (i.e. L3/L2 cache) based on application priority or
79 corresponding cache portion is available.
122 In different systems, the different cache level is supported, e.g. L3 cache or
123 L2 cache. Per cache level cbm can be specified with the `--level LEVEL` option.
133 In different systems, the different cache level is supported, e.g. L3 cache or
134 L2 cache. Per cache level cbm can be specified with the `--level LEVEL` option.
141 cache in a software configurable manner, which can enable workload
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/xen/xen/arch/x86/hvm/
A Demulate.c1032 memset(cache, 0, sizeof (*cache)); in hvmemul_find_mmio_cache()
1037 return cache; in hvmemul_find_mmio_cache()
2635 if ( vio->cache->num_ents > vio->cache->max_ents ) in _hvm_emulate_one()
2990 v->arch.hvm.hvm_io.cache = cache; in hvmemul_cache_init()
2997 struct hvmemul_cache *cache = v->arch.hvm.hvm_io.cache; in hvmemul_cache_disable() local
3000 cache->num_ents = cache->max_ents + 1; in hvmemul_cache_disable()
3007 struct hvmemul_cache *cache = v->arch.hvm.hvm_io.cache; in hvmemul_cache_restore() local
3009 ASSERT(cache->num_ents > cache->max_ents); in hvmemul_cache_restore()
3020 if ( !is_hvm_vcpu(v) || cache->num_ents > cache->max_ents ) in hvmemul_read_cache()
3048 struct hvmemul_cache *cache = v->arch.hvm.hvm_io.cache; in hvmemul_write_cache() local
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A Dstdvga.c114 if ( s->cache != STDVGA_CACHE_UNINITIALIZED ) in stdvga_try_cache_enable()
118 s->cache = STDVGA_CACHE_ENABLED; in stdvga_try_cache_enable()
123 if ( s->cache != STDVGA_CACHE_ENABLED ) in stdvga_cache_disable()
127 s->cache = STDVGA_CACHE_DISABLED; in stdvga_cache_disable()
132 return s->cache == STDVGA_CACHE_ENABLED; in stdvga_cache_is_enabled()
/xen/tools/libfsimage/reiserfs/
A Dfsys_reiserfs.c345 #define BLOCKHEAD(cache) ((struct block_head *) cache) argument
347 #define KEY(cache) ((struct key *) ((char *) cache + BLKH_SIZE)) argument
691 return cache; in read_tree_node()
710 return cache; in read_tree_node()
721 char *cache; in next_key() local
755 cache = ROOT; in next_key()
761 if (! cache) in next_key()
777 if (! cache) in next_key()
811 char *cache; in search_stat() local
821 cache = ROOT; in search_stat()
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/xen/xen/lib/x86/
A Dcpuid.c89 for ( i = 0; i < ARRAY_SIZE(p->cache.raw); ++i ) in x86_cpuid_policy_fill_native()
101 p->cache.subleaf[i] = u.c; in x86_cpuid_policy_fill_native()
109 if ( i == ARRAY_SIZE(p->cache.raw) ) in x86_cpuid_policy_fill_native()
194 memset(p->cache.raw, 0, sizeof(p->cache.raw)); in x86_cpuid_policy_clear_out_of_range_leaves()
197 for ( i = 0; (i < ARRAY_SIZE(p->cache.raw) && in x86_cpuid_policy_clear_out_of_range_leaves()
198 p->cache.subleaf[i].type); ++i ) in x86_cpuid_policy_clear_out_of_range_leaves()
201 zero_leaves(p->cache.raw, i, ARRAY_SIZE(p->cache.raw) - 1); in x86_cpuid_policy_clear_out_of_range_leaves()
318 COPY_LEAF(leaf, subleaf, &p->cache.raw[subleaf]); in x86_cpuid_copy_to_buffer()
320 if ( p->cache.subleaf[subleaf].type == 0 ) in x86_cpuid_copy_to_buffer()
421 if ( data.subleaf >= ARRAY_SIZE(p->cache.raw) ) in x86_cpuid_copy_from_buffer()
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/xen/xen/arch/arm/
A DKconfig129 master interface and an L2 cache.
136 The workaround promotes data cache clean instructions to
137 data cache clean-and-invalidate.
155 cluster is executing a cache maintenance operation to the same
156 address, then this erratum might cause a clean cache line to be
159 The workaround promotes data cache clean instructions to
160 data cache clean-and-invalidate.
173 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
177 the same time as a processor in another cluster is executing a cache
181 The workaround promotes data cache clean instructions to
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/xen/docs/features/
A Dintel_psr_cat_cdp.pandoc35 CAT allows an OS or hypervisor to control allocation of a CPU's shared cache
42 Intel Goldmont processor provides support for control over the L2 cache.
46 the L3 cache in a SW configurable manner, which can enable workload
47 prioritization and tuning of cache capacity to the characteristics of the
66 `-l2`: Show cbm for L2 cache.
68 `-l3`: Show cbm for L3 cache.
82 `-l2`: Specify cbm for L2 cache.
84 `-l3`: Specify cbm for L3 cache.
129 CAT/CDP MSRs, setting different L2 cache accessing patterns from L3 cache is
135 other domains contending for the cache.
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/xen/automation/build/centos/
A D6.dockerfile15 rm -rf /var/cache/yum
51 rm -rf /var/cache/yum
A D7.dockerfile15 rm -rf /var/cache/yum
49 rm -rf /var/cache/yum
/xen/xen/arch/x86/
A Dcpuid.c274 memset(p->cache.raw, 0, sizeof(p->cache.raw)); in recalculate_misc()
675 for ( i = 0; i < ARRAY_SIZE(p->cache.raw); ++i ) in recalculate_cpuid_policy()
677 if ( p->cache.subleaf[i].type >= 1 && in recalculate_cpuid_policy()
678 p->cache.subleaf[i].type <= 3 ) in recalculate_cpuid_policy()
681 p->cache.raw[i].a &= 0xffffc3ffu; in recalculate_cpuid_policy()
682 p->cache.raw[i].d &= 0x00000007u; in recalculate_cpuid_policy()
687 zero_leaves(p->cache.raw, i, ARRAY_SIZE(p->cache.raw) - 1); in recalculate_cpuid_policy()
763 if ( subleaf >= ARRAY_SIZE(p->cache.raw) ) in guest_cpuid()
766 *res = array_access_nospec(p->cache.raw, subleaf); in guest_cpuid()
/xen/xen/arch/arm/arm64/
A DMakefile3 obj-y += cache.o
/xen/tools/tests/cpu-policy/
A Dtest-cpu-policy.c132 .cache.subleaf[0].type = 1, in test_cpuid_serialise_success()
427 .cache.raw[0].a = 0xc2, in test_cpuid_out_of_range_clearing()
440 .cache.raw[0] = { .a = 1, .b = 0xc2 }, in test_cpuid_out_of_range_clearing()
442 .cache.raw[1].b = 0xc2, in test_cpuid_out_of_range_clearing()
/xen/tools/libxc/
A Dxc_cpuid_x86.c592 for ( i = 0; (p->cache.subleaf[i].type && in xc_cpuid_apply_policy()
593 i < ARRAY_SIZE(p->cache.raw)); ++i ) in xc_cpuid_apply_policy()
595 p->cache.subleaf[i].cores_per_package = in xc_cpuid_apply_policy()
596 (p->cache.subleaf[i].cores_per_package << 1) | 1; in xc_cpuid_apply_policy()
597 p->cache.subleaf[i].threads_per_cache = 0; in xc_cpuid_apply_policy()
/xen/automation/build/fedora/
A D29.dockerfile45 rm -rf /var/cache/dnf
/xen/
A Dconfigure1253 --cache-file=FILE cache test results in FILE [disabled]
1254 -C, --config-cache alias for \`--cache-file=config.cache'
1686 { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5
1687 $as_echo "$as_me: loading cache $cache_file" >&6;}
1694 { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5
1695 $as_echo "$as_me: creating cache $cache_file" >&6;}
3603 …ineno-$LINENO}: running $SHELL $ac_sub_configure $ac_sub_configure_args --cache-file=$ac_sub_cache…
3604 $as_echo "$as_me: running $SHELL $ac_sub_configure $ac_sub_configure_args --cache-file=$ac_sub_cach…
A D.gitignore39 autom4te.cache/
42 config.cache
61 stubdom/autom4te.cache/
63 stubdom/config.cache
97 tools/autom4te.cache/
101 tools/config.cache
A DMakefile239 rm -rf config.log config.status config.cache autom4te.cache
/xen/docs/
A Dconfigure1241 --cache-file=FILE cache test results in FILE [disabled]
1242 -C, --config-cache alias for \`--cache-file=config.cache'
1670 { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5
1671 $as_echo "$as_me: loading cache $cache_file" >&6;}
1678 { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5
1679 $as_echo "$as_me: creating cache $cache_file" >&6;}
A DMakefile78 rm -rf $(XEN_ROOT)/config/Docs.mk config.log config.status config.cache \
79 autom4te.cache
/xen/xen/include/asm-x86/hvm/
A Demulate.h123 XFREE(v->arch.hvm.hvm_io.cache); in hvmemul_cache_destroy()
A Dvcpu.h79 struct hvmemul_cache *cache; member
A Dio.h153 enum stdvga_cache_state cache; member
/xen/xen/tools/kconfig/
A DMakefile115 -o cache_dir=$(abspath $(obj)/tests/.cache) \
117 clean-files += tests/.cache
/xen/xen/include/asm-arm/
A Dhsr.h130 unsigned long cache:1; /* Cache Maintenance */ member
/xen/tools/
A DMakefile92 config.cache autom4te.cache

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