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Searched refs:dmar_readq (Results 1 – 4 of 4) sorted by relevance

/xen/xen/drivers/passthrough/vtd/
A Dutils.c60 printk(" CAP = %"PRIx64"\n", cap = dmar_readq(iommu->reg, DMAR_CAP_REG)); in print_iommu_regs()
66 dmar_readq(iommu->reg, cap_fault_reg_offset(cap))); in print_iommu_regs()
68 dmar_readq(iommu->reg, cap_fault_reg_offset(cap) + 8)); in print_iommu_regs()
70 printk(" ECAP = %"PRIx64"\n", dmar_readq(iommu->reg, DMAR_ECAP_REG)); in print_iommu_regs()
73 printk(" RTADDR = %"PRIx64"\n", dmar_readq(iommu->reg,DMAR_RTADDR_REG)); in print_iommu_regs()
74 printk(" CCMD = %"PRIx64"\n", dmar_readq(iommu->reg, DMAR_CCMD_REG)); in print_iommu_regs()
207 uint64_t irta = dmar_readq(iommu->reg, DMAR_IRTA_REG); in vtd_dump_iommu_info()
A Dqinval.c40 val = dmar_readq(iommu->reg, DMAR_IQA_REG); in print_qi_regs()
43 val = dmar_readq(iommu->reg, DMAR_IQH_REG); in print_qi_regs()
46 val = dmar_readq(iommu->reg, DMAR_IQT_REG); in print_qi_regs()
54 tail = dmar_readq(iommu->reg, DMAR_IQT_REG); in qinval_next_index()
59 ( dmar_readq(iommu->reg, DMAR_IQH_REG) >> QINVAL_INDEX_SHIFT ) ) in qinval_next_index()
306 (void)dmar_readq(iommu->reg, DMAR_CAP_REG); in queue_invalidate_iec_sync()
A Diommu.c380 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, dmar_readq, in flush_context_reg()
460 IOMMU_WAIT_OP(iommu, (tlb_offset + 8), dmar_readq, in flush_iotlb_reg()
971 guest_addr = dmar_readq(iommu->reg, reg + in __do_iommu_page_fault()
1192 iommu->cap = dmar_readq(iommu->reg, DMAR_CAP_REG); in iommu_alloc()
1193 iommu->ecap = dmar_readq(iommu->reg, DMAR_ECAP_REG); in iommu_alloc()
2076 val = dmar_readq(iommu->reg, cap_fault_reg_offset(iommu->cap) + 8); in clear_fault_bits()
A Diommu.h54 #define dmar_readq(dmar, reg) readq((dmar) + (reg)) macro

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