Home
last modified time | relevance | path

Searched refs:hi (Results 1 – 25 of 42) sorted by relevance

12

/xen/xen/include/asm-x86/x86_64/
A Dsystem.h20 struct { uint64_t lo, hi; }; in __cmpxchg16b() member
28 : "=d" (prev.hi), "=a" (prev.lo), in __cmpxchg16b()
30 : "c" (new.hi), "b" (new.lo), "d" (old.hi), "a" (old.lo) ); in __cmpxchg16b()
39 struct { uint64_t lo, hi; }; in cmpxchg16b_local_() member
47 : "=d" (prev.hi), "=a" (prev.lo), in cmpxchg16b_local_()
49 : "c" (new.hi), "b" (new.lo), "d" (old.hi), "a" (old.lo) ); in cmpxchg16b_local_()
/xen/xen/drivers/passthrough/vtd/
A Diommu.h205 u64 hi; member
212 #define context_address_width(c) ((c).hi & 7)
213 #define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
231 do {(c).hi &= 0xfffffff8; (c).hi |= (val) & 7;} while(0)
288 struct { u64 lo, hi; }; member
376 u64 hi; member
390 }hi; member
407 }hi; member
422 }hi; member
435 }hi; member
[all …]
A Dqinval.c99 qinval_entry->q.cc_inv_dsc.hi.res = 0; in queue_invalidate_context_sync()
134 qinval_entry->q.iotlb_inv_dsc.hi.am = am; in queue_invalidate_iotlb_sync()
135 qinval_entry->q.iotlb_inv_dsc.hi.ih = ih; in queue_invalidate_iotlb_sync()
136 qinval_entry->q.iotlb_inv_dsc.hi.res_1 = 0; in queue_invalidate_iotlb_sync()
137 qinval_entry->q.iotlb_inv_dsc.hi.addr = addr >> PAGE_SHIFT_4K; in queue_invalidate_iotlb_sync()
171 qinval_entry->q.inv_wait_dsc.hi.saddr = virt_to_maddr(this_poll_slot); in queue_invalidate_wait()
261 qinval_entry->q.dev_iotlb_inv_dsc.hi.size = size; in qinval_device_iotlb_sync()
262 qinval_entry->q.dev_iotlb_inv_dsc.hi.res_1 = 0; in qinval_device_iotlb_sync()
263 qinval_entry->q.dev_iotlb_inv_dsc.hi.addr = addr >> PAGE_SHIFT_4K; in qinval_device_iotlb_sync()
294 qinval_entry->q.iec_inv_dsc.hi.res = 0; in queue_invalidate_iec_sync()
A Dintremap.c209 write_atomic(&entry->hi, new_ire->hi); in update_irte()
210 else if ( entry->hi == new_ire->hi ) in update_irte()
/xen/xen/include/asm-x86/
A Dmsr.h35 __u32 lo, hi; in wrmsrl() local
37 hi = (__u32)(val >> 32); in wrmsrl()
38 wrmsr(msr, lo, hi); in wrmsrl()
61 uint32_t lo, hi; in wrmsr_safe() local
63 hi = (uint32_t)(val >> 32); in wrmsr_safe()
72 : "c" (msr), "a" (lo), "d" (hi), "0" (0), "i" (-EFAULT)); in wrmsr_safe()
A Dxstate.h114 uint32_t lo, hi; in xgetbv() local
118 : "=a" (lo), "=d" (hi) : "c" (index) ); in xgetbv()
120 return lo | ((uint64_t)hi << 32); in xgetbv()
A Dapic.h117 u32 lo, hi; in apic_icr_read() local
124 hi = apic_mem_read(APIC_ICR2); in apic_icr_read()
127 return ((u64)lo) | (((u64)hi) << 32); in apic_icr_read()
A Dhypercall.h165 unsigned int va, u32 lo, u32 hi, unsigned int flags);
168 unsigned int va, u32 lo, u32 hi, unsigned int flags, domid_t domid);
A Dmtrr.h75 extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
/xen/xen/arch/x86/cpu/
A Damd.c53 unsigned int *hi) in rdmsr_amd_safe() argument
63 : "=a" (*lo), "=d" (*hi), "=r" (err) in rdmsr_amd_safe()
70 unsigned int hi) in wrmsr_amd_safe() argument
146 unsigned int hi, lo; in _probe_mask_msr() local
150 if ((rdmsr_amd_safe(msr, &lo, &hi) == 0) && in _probe_mask_msr()
151 (wrmsr_amd_safe(msr, lo, hi) == 0)) in _probe_mask_msr()
154 return ((uint64_t)hi << 32) | lo; in _probe_mask_msr()
539 uint64_t hi, lo, val; in amd_log_freq() local
626 !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) in amd_log_freq()
629 else if (h && !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) in amd_log_freq()
[all …]
A Dintel.c343 unsigned long lo, hi; in Intel_errata_workarounds() local
346 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi); in Intel_errata_workarounds()
351 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); in Intel_errata_workarounds()
/xen/xen/common/sched/
A Dcompat.c42 int compat_set_timer_op(u32 lo, s32 hi) in compat_set_timer_op() argument
44 return do_set_timer_op(((s64)hi << 32) | lo); in compat_set_timer_op()
/xen/tools/tests/x86_emulator/
A Dx86-emulate.c200 uint32_t lo, hi; in emul_test_read_xcr() local
218 asm ( "xgetbv" : "=a" (lo), "=d" (hi) : "c" (reg) ); in emul_test_read_xcr()
219 *val = lo | ((uint64_t)hi << 32); in emul_test_read_xcr()
A Dsimd-clmul.c79 vec_t x = {}, y, z, lo, hi; in clmul_test() local
120 z = hi = clmul_hh(x, src); in clmul_test()
126 vec_t h = lane_shr_v(hi, 2 * j); in clmul_test()
A Dx86-emulate.h116 uint32_t lo, hi; in xgetbv() local
118 asm ( ".byte 0x0f, 0x01, 0xd0" : "=a" (lo), "=d" (hi) : "c" (xcr) ); in xgetbv()
120 return ((uint64_t)hi << 32) | lo; in xgetbv()
/xen/xen/drivers/vpci/
A Dheader.c359 bool hi = false; in bar_write() local
365 hi = true; in bar_write()
373 if ( val != (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) in bar_write()
377 bar - pdev->vpci->header.bars + hi); in bar_write()
386 bar->addr &= ~(0xffffffffull << (hi ? 32 : 0)); in bar_write()
387 bar->addr |= (uint64_t)val << (hi ? 32 : 0); in bar_write()
390 if ( !hi ) in bar_write()
/xen/xen/arch/x86/cpu/mtrr/
A Dgeneric.c360 uint32_t lo, hi, base_lo, base_hi, mask_lo, mask_hi; in set_mtrr_var_ranges() local
366 hi = (uint32_t)(msr_content >> 32); in set_mtrr_var_ranges()
372 hi &= size_and_mask >> (32 - PAGE_SHIFT); in set_mtrr_var_ranges()
375 if ((base_lo != lo) || (base_hi != hi)) { in set_mtrr_var_ranges()
382 hi = (uint32_t)(msr_content >> 32); in set_mtrr_var_ranges()
388 hi &= size_and_mask >> (32 - PAGE_SHIFT); in set_mtrr_var_ranges()
391 if ((mask_lo != lo) || (mask_hi != hi)) { in set_mtrr_var_ranges()
/xen/xen/arch/x86/acpi/cpufreq/
A Dpowernow.c147 u32 hi, lo, fid, did; in amd_fixup_frequency() local
154 rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi); in amd_fixup_frequency()
159 if (!(hi & (1U << 31))) in amd_fixup_frequency()
/xen/tools/misc/
A Dxen-hvmctx.c81 uint16_t hi; member
87 uint64_t hi; member
121 i, r->mm[i].hi, r->mm[i].lo, in dump_fpu()
126 i, r->xmm[i].hi, r->xmm[i].lo); in dump_fpu()
/xen/xen/arch/x86/genapic/
A Dx2apic.c271 u32 lo, hi; in check_x2apic_preenabled() local
277 rdmsr(MSR_APIC_BASE, lo, hi); in check_x2apic_preenabled()
/xen/xen/include/acpi/
A Dactypes.h289 u32 hi; member
299 u32 hi; member
/xen/xen/include/xen/
A Dhypercall.h198 s32 hi);
/xen/xen/arch/arm/
A Dvcpreg.c77 bool read, bool hi) \
84 if ( hi ) /* reg[63:32] is AArch32 register hireg */ \
/xen/xen/drivers/passthrough/amd/
A Diommu_map.c164 #define GCR3_MASK(hi, lo) (((1ul << ((hi) + 1)) - 1) & ~((1ul << (lo)) - 1)) in iommu_dte_set_guest_cr3() argument
/xen/xen/crypto/
A Dvmac.c107 ({ uint32_t hi, lo, *_p = (uint32_t *)(p); \
109 asm volatile ("lwbrx %0, %1, %2" : "=r"(hi) : "b%"(4), "r"(_p) ); \
110 ((uint64_t)hi << 32) | (uint64_t)lo; } )
117 ({ uint32_t hi, lo, *_p = (uint32_t *)(p); \
119 asm volatile ("lwbrx %0, %1, %2" : "=r"(hi) : "b%"(4), "r"(_p) ); \
120 ((uint64_t)hi << 32) | (uint64_t)lo; } )

Completed in 65 milliseconds

12