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Searched refs:midr (Results 1 – 7 of 7) sorted by relevance

/xen/xen/include/asm-arm/
A Dprocessor.h16 #define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK) argument
19 #define MIDR_PARTNUM(midr) \ argument
20 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
23 #define MIDR_ARCHITECTURE(midr) \ argument
24 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
27 #define MIDR_VARIANT(midr) \ argument
28 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
31 #define MIDR_IMPLEMENTOR(midr) \ argument
32 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
42 #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ argument
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A Dcpufeature.h125 } midr; member
/xen/xen/arch/arm/
A Dsmpboot.c322 current_cpu_data.midr.bits != boot_cpu_data.midr.bits ) in start_secondary()
326 smp_processor_id(), current_cpu_data.midr.bits, in start_secondary()
327 boot_cpu_data.midr.bits); in start_secondary()
A Dsetup.c110 if ( c->midr.implementer < ARRAY_SIZE(processor_implementers) && in processor_id()
111 processor_implementers[c->midr.implementer] ) in processor_id()
112 implementer = processor_implementers[c->midr.implementer]; in processor_id()
114 if ( c->midr.architecture != 0xf ) in processor_id()
116 c->midr.architecture); in processor_id()
119 c->midr.bits, implementer, in processor_id()
120 c->midr.variant, c->midr.part_number, c->midr.revision); in processor_id()
A Dcpufeature.c102 c->midr.bits = READ_SYSREG32(MIDR_EL1); in identify_cpu()
A Dvcpreg.c469 val |= ((current_cpu_data.midr.bits >> 20) & 0xf) | in do_cp14_32()
470 (current_cpu_data.midr.bits & 0xf); in do_cp14_32()
A Dcpuerrata.c386 return MIDR_IS_CPU_MODEL_RANGE(current_cpu_data.midr.bits, entry->midr_model, in is_affected_midr_range()

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