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Searched refs:msr_content (Results 1 – 25 of 35) sorted by relevance

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/xen/xen/arch/x86/oprofile/
A Dop_model_ppro.c51 #define CTRL_READ(msr_content,msrs,c) do {rdmsrl((msrs->controls[(c)].addr), (msr_content));} while… argument
79 uint64_t msr_content; in ppro_setup_ctrs() local
101 CTRL_READ(msr_content, msrs, i); in ppro_setup_ctrs()
102 CTRL_CLEAR(msr_content); in ppro_setup_ctrs()
118 CTRL_CLEAR(msr_content); in ppro_setup_ctrs()
119 CTRL_SET_ENABLE(msr_content); in ppro_setup_ctrs()
175 uint64_t msr_content; in ppro_start() local
181 CTRL_SET_ACTIVE(msr_content); in ppro_start()
195 uint64_t msr_content; in ppro_stop() local
202 CTRL_SET_INACTIVE(msr_content); in ppro_stop()
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A Dop_model_athlon.c36 #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr, (msr_content));} while (0) argument
40 #define CTRL_READ(msr_content,msrs,c) do {rdmsrl(msrs->controls[(c)].addr, (msr_content));} while (… argument
41 #define CTRL_WRITE(msr_content,msrs,c) do {wrmsrl(msrs->controls[(c)].addr, (msr_content));} while … argument
199 uint64_t msr_content; in athlon_setup_ctrs() local
207 CTRL_CLEAR(msr_content); in athlon_setup_ctrs()
224 CTRL_CLEAR(msr_content); in athlon_setup_ctrs()
225 CTRL_SET_ENABLE(msr_content); in athlon_setup_ctrs()
316 uint64_t msr_content; in athlon_check_ctrs() local
391 uint64_t msr_content; in athlon_start() local
397 CTRL_SET_ACTIVE(msr_content); in athlon_start()
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A Dop_model_p4.c536 uint64_t msr_content; in p4_setup_ctrs() local
551 CCCR_CLEAR(msr_content); in p4_setup_ctrs()
559 CCCR_CLEAR(msr_content); in p4_setup_ctrs()
617 uint64_t msr_content; in p4_check_ctrs() local
649 CCCR_READ(msr_content, real); in p4_check_ctrs()
654 CCCR_CLEAR_OVF(msr_content); in p4_check_ctrs()
655 CCCR_WRITE(msr_content, real); in p4_check_ctrs()
671 uint64_t msr_content; in p4_start() local
680 CCCR_SET_ENABLE(msr_content); in p4_start()
689 uint64_t msr_content; in p4_stop() local
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A Dop_x86_model.h42 void (*load_msr)(struct vcpu * const v, int type, int index, u64 *msr_content);
43 void (*save_msr)(struct vcpu * const v, int type, int index, u64 msr_content);
A Dnmi_int.c57 int passive_domain_do_rdmsr(unsigned int msr, uint64_t *msr_content) in passive_domain_do_rdmsr() argument
64 model->load_msr(current, type, index, msr_content); in passive_domain_do_rdmsr()
68 int passive_domain_do_wrmsr(unsigned int msr, uint64_t msr_content) in passive_domain_do_wrmsr() argument
75 model->save_msr(current, type, index, msr_content); in passive_domain_do_wrmsr()
/xen/xen/arch/x86/cpu/
A Dvpmu_intel.c124 val = msr_content; in handle_pmc_quirk()
136 val = msr_content >> 32; in handle_pmc_quirk()
562 if ( msr_content ) in core2_vpmu_do_wrmsr()
576 msr_content); in core2_vpmu_do_wrmsr()
599 if ( msr_content != 0 ) in core2_vpmu_do_wrmsr()
601 u64 val = msr_content; in core2_vpmu_do_wrmsr()
678 wrmsrl(msr, msr_content); in core2_vpmu_do_wrmsr()
709 *msr_content = 0; in core2_vpmu_do_rdmsr()
784 u64 msr_content; in core2_vpmu_do_interrupt() local
789 if ( msr_content ) in core2_vpmu_do_interrupt()
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A Dcentaur.c19 uint64_t msr_content; in init_c3() local
27 rdmsrl(MSR_VIA_FCR, msr_content); in init_c3()
29 wrmsrl(MSR_VIA_FCR, msr_content | ACE_FCR); in init_c3()
35 rdmsrl(MSR_VIA_RNG, msr_content); in init_c3()
37 wrmsrl(MSR_VIA_RNG, msr_content | RNG_ENABLE); in init_c3()
A Dvpmu_amd.c325 static void context_update(unsigned int msr, u64 msr_content) in context_update() argument
344 ctrl_regs[i] = msr_content; in context_update()
349 counter_regs[i] = msr_content; in context_update()
355 static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content, in amd_vpmu_do_wrmsr() argument
366 ((msr_content & CTRL_RSVD_MASK) != ctrl_rsvd[idx]) ) in amd_vpmu_do_wrmsr()
371 !is_guest_mode(msr_content) ) in amd_vpmu_do_wrmsr()
373 set_guest_mode(msr_content); in amd_vpmu_do_wrmsr()
407 context_update(msr, msr_content); in amd_vpmu_do_wrmsr()
410 wrmsrl(msr, msr_content); in amd_vpmu_do_wrmsr()
414 static int amd_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content) in amd_vpmu_do_rdmsr() argument
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/xen/xen/arch/x86/
A Dapic.c309 uint64_t msr_content; in disable_local_APIC() local
310 rdmsrl(MSR_APIC_BASE, msr_content); in disable_local_APIC()
317 uint64_t msr_content; in disable_local_APIC() local
333 msr_content |= APIC_BASE_EXTD; in disable_local_APIC()
484 uint64_t msr_content; in __enable_x2apic() local
486 rdmsrl(MSR_APIC_BASE, msr_content); in __enable_x2apic()
487 if ( !(msr_content & APIC_BASE_EXTD) ) in __enable_x2apic()
490 msr_content = (uint32_t)msr_content; in __enable_x2apic()
710 uint64_t msr_content; in lapic_resume() local
795 uint64_t msr_content; in detect_init_APIC() local
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A Dnmi.c522 uint64_t msr_content; in nmi_watchdog_tick() local
527 rdmsrl(MSR_P4_IQ_CCCR0, msr_content); in nmi_watchdog_tick()
528 if ( !(msr_content & P4_CCCR_OVF) ) in nmi_watchdog_tick()
543 rdmsrl(MSR_P6_PERFCTR(0), msr_content); in nmi_watchdog_tick()
544 if ( msr_content & (1ULL << (nmi_p6_event_width - 1)) ) in nmi_watchdog_tick()
555 rdmsrl(MSR_K7_PERFCTR0, msr_content); in nmi_watchdog_tick()
556 if ( msr_content & (1ULL << K7_EVENT_WIDTH) ) in nmi_watchdog_tick()
/xen/xen/arch/x86/genapic/
A Dx2apic.c99 uint64_t msr_content; in send_IPI_mask_x2apic_phys() local
119 msr_content = cpu_physical_id(cpu); in send_IPI_mask_x2apic_phys()
120 msr_content = (msr_content << 32) | APIC_DM_FIXED | in send_IPI_mask_x2apic_phys()
122 apic_wrmsr(APIC_ICR, msr_content); in send_IPI_mask_x2apic_phys()
144 uint64_t msr_content = 0; in send_IPI_mask_x2apic_cluster() local
151 msr_content |= per_cpu(cpu_2_logical_apicid, cpu); in send_IPI_mask_x2apic_cluster()
154 BUG_ON(!(msr_content & 0xffff)); in send_IPI_mask_x2apic_cluster()
155 msr_content = (msr_content << 32) | APIC_DM_FIXED | in send_IPI_mask_x2apic_cluster()
157 apic_wrmsr(APIC_ICR, msr_content); in send_IPI_mask_x2apic_cluster()
/xen/xen/arch/x86/cpu/mcheck/
A Dmce_intel.c60 uint64_t msr_content; in intel_thermal_interrupt() local
75 *this_last_state = msr_content & MCE_RING; in intel_thermal_interrupt()
76 if ( msr_content & MCE_RING ) in intel_thermal_interrupt()
111 uint64_t msr_content; in intel_init_thermal() local
140 if ( (msr_content & (1ULL<<3)) in intel_init_thermal()
722 uint64_t msr_content; in intel_enable_lmce() local
749 uint64_t msr_content; in intel_init_mca() local
759 if ( msr_content & MCG_SER_P ) in intel_init_mca()
762 if ( msr_content & MCG_EXT_P ) in intel_init_mca()
822 uint64_t msr_content; in intel_init_mce() local
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/xen/xen/arch/x86/cpu/mtrr/
A Dgeneric.c97 uint64_t msr_content; in get_mtrr_state() local
107 rdmsrl(MSR_MTRRcap, msr_content); in get_mtrr_state()
114 rdmsrl(MSR_MTRRdefType, msr_content); in get_mtrr_state()
279 uint64_t msr_content, val; in set_fixed_range() local
281 rdmsrl(msr, msr_content); in set_fixed_range()
284 if (msr_content != val) { in set_fixed_range()
361 uint64_t msr_content; in set_mtrr_var_ranges() local
365 lo = (uint32_t)msr_content; in set_mtrr_var_ranges()
366 hi = (uint32_t)(msr_content >> 32); in set_mtrr_var_ranges()
381 lo = (uint32_t)msr_content; in set_mtrr_var_ranges()
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/xen/xen/include/asm-x86/
A Dvpmu.h42 int (*do_wrmsr)(unsigned int msr, uint64_t msr_content,
44 int (*do_rdmsr)(unsigned int msr, uint64_t *msr_content);
108 int vpmu_do_msr(unsigned int msr, uint64_t *msr_content,
117 static inline int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content, in vpmu_do_wrmsr() argument
120 return vpmu_do_msr(msr, &msr_content, supported, 1); in vpmu_do_wrmsr()
122 static inline int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content) in vpmu_do_rdmsr() argument
124 return vpmu_do_msr(msr, msr_content, 0, 0); in vpmu_do_rdmsr()
A Dxenoprof.h68 int passive_domain_do_rdmsr(unsigned int msr, uint64_t *msr_content);
69 int passive_domain_do_wrmsr(unsigned int msr, uint64_t msr_content);
75 uint64_t *msr_content) in passive_domain_do_rdmsr() argument
81 uint64_t msr_content) in passive_domain_do_wrmsr() argument
A Dapic.h70 static __inline void apic_wrmsr(unsigned long reg, uint64_t msr_content) in apic_wrmsr() argument
76 wrmsrl(APIC_MSR_BASE + (reg >> 4), msr_content); in apic_wrmsr()
81 uint64_t msr_content; in apic_rdmsr() local
86 rdmsrl(APIC_MSR_BASE + (reg >> 4), msr_content); in apic_rdmsr()
87 return msr_content; in apic_rdmsr()
A Dmtrr.h90 uint32_t msr, uint64_t msr_content);
92 uint32_t row, uint64_t msr_content);
94 uint64_t msr_content);
/xen/xen/arch/x86/hvm/svm/
A Dsvm.c1504 uint64_t msr_content; in svm_init_erratum_383() local
1579 uint64_t msr_content; in _svm_cpu_up() local
1826 *msr_content = vmcb->star; in svm_msr_read_intercept()
1830 *msr_content = vmcb->lstar; in svm_msr_read_intercept()
1834 *msr_content = vmcb->cstar; in svm_msr_read_intercept()
1868 *msr_content = 0; in svm_msr_read_intercept()
1948 msr, *msr_content); in svm_msr_read_intercept()
2027 vmcb->star = msr_content; in svm_msr_write_intercept()
2134 uint64_t msr_content = 0; in svm_do_msr_access() local
2316 uint64_t msr_content; in svm_is_erratum_383() local
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/xen/xen/arch/x86/cpu/microcode/
A Dintel.c122 uint64_t msr_content; in collect_cpu_info() local
126 rdmsrl(MSR_IA32_PLATFORM_ID, msr_content); in collect_cpu_info()
127 csig->pf = 1 << ((msr_content >> 50) & 7); in collect_cpu_info()
134 rdmsrl(MSR_IA32_UCODE_REV, msr_content); in collect_cpu_info()
135 csig->rev = (uint32_t)(msr_content >> 32); in collect_cpu_info()
263 uint64_t msr_content; in apply_microcode() local
281 rdmsrl(MSR_IA32_UCODE_REV, msr_content); in apply_microcode()
282 sig->rev = rev = msr_content >> 32; in apply_microcode()
/xen/xen/arch/x86/hvm/
A Dmtrr.c396 uint64_t msr_content) in mtrr_def_type_msr_set() argument
398 uint8_t def_type = msr_content & 0xff; in mtrr_def_type_msr_set()
408 if ( unlikely(msr_content && (msr_content & ~0xcffUL)) ) in mtrr_def_type_msr_set()
411 msr_content); in mtrr_def_type_msr_set()
432 if ( fixed_range_base[row] != msr_content ) in mtrr_fix_range_msr_set()
434 uint8_t *range = (uint8_t*)&msr_content; in mtrr_fix_range_msr_set()
441 fixed_range_base[row] = msr_content; in mtrr_fix_range_msr_set()
464 if ( var_range_base[index] == msr_content ) in mtrr_var_range_msr_set()
476 if ( unlikely(msr_content & msr_mask) ) in mtrr_var_range_msr_set()
479 msr_content); in mtrr_var_range_msr_set()
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A Dvlapic.c987 if ( msr_content & ~APIC_TPRI_MASK ) in guest_wrmsr_x2apic()
992 if ( msr_content & ~(APIC_VECTOR_MASK | APIC_SPIV_APIC_ENABLED | in guest_wrmsr_x2apic()
1000 if ( msr_content & ~(LVT_MASK | APIC_TIMER_MODE_MASK) ) in guest_wrmsr_x2apic()
1007 if ( msr_content & ~(LVT_MASK | APIC_MODE_MASK) ) in guest_wrmsr_x2apic()
1013 if ( msr_content & ~LINT_MASK ) in guest_wrmsr_x2apic()
1018 if ( msr_content & ~LVT_MASK ) in guest_wrmsr_x2apic()
1026 if ( msr_content & ~APIC_TDR_DIV_1 ) in guest_wrmsr_x2apic()
1035 vlapic_set_reg(vlapic, APIC_ICR2, msr_content >> 32); in guest_wrmsr_x2apic()
1039 if ( msr_content & ~APIC_VECTOR_MASK ) in guest_wrmsr_x2apic()
1042 msr_content = APIC_DEST_SELF | (msr_content & APIC_VECTOR_MASK); in guest_wrmsr_x2apic()
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/xen/xen/arch/x86/acpi/cpufreq/
A Dpowernow.c64 uint64_t msr_content; in update_cpb() local
66 rdmsrl(MSR_K8_HWCR, msr_content); in update_cpb()
69 msr_content &= ~MSR_HWCR_CPBDIS_MASK; in update_cpb()
71 msr_content |= MSR_HWCR_CPBDIS_MASK; in update_cpb()
73 wrmsrl(MSR_K8_HWCR, msr_content); in update_cpb()
179 uint64_t msr_content; in get_cpu_data() local
182 rdmsrl(MSR_PSTATE_CUR_LIMIT, msr_content); in get_cpu_data()
183 data->max_hw_pstate = (msr_content & HW_PSTATE_MAX_MASK) >> in get_cpu_data()
/xen/xen/arch/x86/hvm/vmx/
A Dvmx.c2972 *msr_content = rdgsshadow(); in vmx_msr_read_intercept()
3031 *msr_content = 0; in vmx_msr_read_intercept()
3043 msr, *msr_content); in vmx_msr_read_intercept()
3204 wrgsshadow(msr_content); in vmx_msr_write_intercept()
3209 v->arch.hvm.vmx.star = msr_content; in vmx_msr_write_intercept()
3210 wrmsrl(MSR_STAR, msr_content); in vmx_msr_write_intercept()
3216 v->arch.hvm.vmx.lstar = msr_content; in vmx_msr_write_intercept()
3217 wrmsrl(MSR_LSTAR, msr_content); in vmx_msr_write_intercept()
3248 if ( msr_content & rsvd ) in vmx_msr_write_intercept()
4107 uint64_t msr_content = 0; in vmx_vmexit_handler() local
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/xen/xen/arch/x86/x86_64/
A Dmmconfig-shared.c143 uint64_t base, msr_content; in pci_mmcfg_amd_fam10h() local
151 if (rdmsr_safe(address, msr_content)) in pci_mmcfg_amd_fam10h()
155 if (!(msr_content & FAM10H_MMIO_CONF_ENABLE)) in pci_mmcfg_amd_fam10h()
158 base = msr_content & in pci_mmcfg_amd_fam10h()
161 busnbits = (msr_content >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & in pci_mmcfg_amd_fam10h()
/xen/xen/include/asm-x86/hvm/
A Dsupport.h153 unsigned int msr, uint64_t *msr_content);
155 unsigned int msr, uint64_t msr_content, bool may_defer);

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