1 #ifndef __ASM_ARM_HSR_H 2 #define __ASM_ARM_HSR_H 3 4 #include <xen/types.h> 5 6 #if defined(CONFIG_ARM_64) 7 # include <asm/arm64/hsr.h> 8 #endif 9 10 /* HSR data abort size definition */ 11 enum dabt_size { 12 DABT_BYTE = 0, 13 DABT_HALF_WORD = 1, 14 DABT_WORD = 2, 15 DABT_DOUBLE_WORD = 3, 16 }; 17 18 union hsr { 19 uint32_t bits; 20 struct { 21 unsigned long iss:25; /* Instruction Specific Syndrome */ 22 unsigned long len:1; /* Instruction length */ 23 unsigned long ec:6; /* Exception Class */ 24 }; 25 26 /* Common to all conditional exception classes (0x0N, except 0x00). */ 27 struct hsr_cond { 28 unsigned long iss:20; /* Instruction Specific Syndrome */ 29 unsigned long cc:4; /* Condition Code */ 30 unsigned long ccvalid:1;/* CC Valid */ 31 unsigned long len:1; /* Instruction length */ 32 unsigned long ec:6; /* Exception Class */ 33 } cond; 34 35 struct hsr_wfi_wfe { 36 unsigned long ti:1; /* Trapped instruction */ 37 unsigned long sbzp:19; 38 unsigned long cc:4; /* Condition Code */ 39 unsigned long ccvalid:1;/* CC Valid */ 40 unsigned long len:1; /* Instruction length */ 41 unsigned long ec:6; /* Exception Class */ 42 } wfi_wfe; 43 44 /* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */ 45 struct hsr_cp32 { 46 unsigned long read:1; /* Direction */ 47 unsigned long crm:4; /* CRm */ 48 unsigned long reg:5; /* Rt */ 49 unsigned long crn:4; /* CRn */ 50 unsigned long op1:3; /* Op1 */ 51 unsigned long op2:3; /* Op2 */ 52 unsigned long cc:4; /* Condition Code */ 53 unsigned long ccvalid:1;/* CC Valid */ 54 unsigned long len:1; /* Instruction length */ 55 unsigned long ec:6; /* Exception Class */ 56 } cp32; /* HSR_EC_CP15_32, CP14_32, CP10 */ 57 58 struct hsr_cp64 { 59 unsigned long read:1; /* Direction */ 60 unsigned long crm:4; /* CRm */ 61 unsigned long reg1:5; /* Rt1 */ 62 unsigned long reg2:5; /* Rt2 */ 63 unsigned long sbzp2:1; 64 unsigned long op1:4; /* Op1 */ 65 unsigned long cc:4; /* Condition Code */ 66 unsigned long ccvalid:1;/* CC Valid */ 67 unsigned long len:1; /* Instruction length */ 68 unsigned long ec:6; /* Exception Class */ 69 } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */ 70 71 struct hsr_cp { 72 unsigned long coproc:4; /* Number of coproc accessed */ 73 unsigned long sbz0p:1; 74 unsigned long tas:1; /* Trapped Advanced SIMD */ 75 unsigned long res0:14; 76 unsigned long cc:4; /* Condition Code */ 77 unsigned long ccvalid:1;/* CC Valid */ 78 unsigned long len:1; /* Instruction length */ 79 unsigned long ec:6; /* Exception Class */ 80 } cp; /* HSR_EC_CP */ 81 82 /* 83 * This encoding is valid only for ARMv8 (ARM DDI 0487B.a, pages D7-2271 and 84 * G6-4957). On ARMv7, encoding ISS for EC=0x13 is defined as UNK/SBZP 85 * (ARM DDI 0406C.c page B3-1431). UNK/SBZP means that hardware implements 86 * this field as Read-As-Zero. ARMv8 is backwards compatible with ARMv7: 87 * reading CCKNOWNPASS on ARMv7 will return 0, which means that condition 88 * check was passed or instruction was unconditional. 89 */ 90 struct hsr_smc32 { 91 unsigned long res0:19; /* Reserved */ 92 unsigned long ccknownpass:1; /* Instruction passed conditional check */ 93 unsigned long cc:4; /* Condition Code */ 94 unsigned long ccvalid:1;/* CC Valid */ 95 unsigned long len:1; /* Instruction length */ 96 unsigned long ec:6; /* Exception Class */ 97 } smc32; /* HSR_EC_SMC32 */ 98 99 #ifdef CONFIG_ARM_64 100 struct hsr_sysreg { 101 unsigned long read:1; /* Direction */ 102 unsigned long crm:4; /* CRm */ 103 unsigned long reg:5; /* Rt */ 104 unsigned long crn:4; /* CRn */ 105 unsigned long op1:3; /* Op1 */ 106 unsigned long op2:3; /* Op2 */ 107 unsigned long op0:2; /* Op0 */ 108 unsigned long res0:3; 109 unsigned long len:1; /* Instruction length */ 110 unsigned long ec:6; 111 } sysreg; /* HSR_EC_SYSREG */ 112 #endif 113 114 struct hsr_iabt { 115 unsigned long ifsc:6; /* Instruction fault status code */ 116 unsigned long res0:1; /* RES0 */ 117 unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ 118 unsigned long res1:1; /* RES0 */ 119 unsigned long eat:1; /* External abort type */ 120 unsigned long fnv:1; /* FAR not Valid */ 121 unsigned long res2:14; 122 unsigned long len:1; /* Instruction length */ 123 unsigned long ec:6; /* Exception Class */ 124 } iabt; /* HSR_EC_INSTR_ABORT_* */ 125 126 struct hsr_dabt { 127 unsigned long dfsc:6; /* Data Fault Status Code */ 128 unsigned long write:1; /* Write / not Read */ 129 unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ 130 unsigned long cache:1; /* Cache Maintenance */ 131 unsigned long eat:1; /* External Abort Type */ 132 unsigned long fnv:1; /* FAR not Valid */ 133 #ifdef CONFIG_ARM_32 134 unsigned long sbzp0:5; 135 #else 136 unsigned long sbzp0:3; 137 unsigned long ar:1; /* Acquire Release */ 138 unsigned long sf:1; /* Sixty Four bit register */ 139 #endif 140 unsigned long reg:5; /* Register */ 141 unsigned long sign:1; /* Sign extend */ 142 unsigned long size:2; /* Access Size */ 143 unsigned long valid:1; /* Syndrome Valid */ 144 unsigned long len:1; /* Instruction length */ 145 unsigned long ec:6; /* Exception Class */ 146 } dabt; /* HSR_EC_DATA_ABORT_* */ 147 148 /* Contain the common bits between DABT and IABT */ 149 struct hsr_xabt { 150 unsigned long fsc:6; /* Fault status code */ 151 unsigned long pad1:1; /* Not common */ 152 unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ 153 unsigned long pad2:1; /* Not common */ 154 unsigned long eat:1; /* External abort type */ 155 unsigned long fnv:1; /* FAR not Valid */ 156 unsigned long pad3:14; /* Not common */ 157 unsigned long len:1; /* Instruction length */ 158 unsigned long ec:6; /* Exception Class */ 159 } xabt; 160 161 #ifdef CONFIG_ARM_64 162 struct hsr_brk { 163 unsigned long comment:16; /* Comment */ 164 unsigned long res0:9; 165 unsigned long len:1; /* Instruction length */ 166 unsigned long ec:6; /* Exception Class */ 167 } brk; 168 #endif 169 }; 170 171 /* HSR.EC == HSR_CP{15,14,10}_32 */ 172 #define HSR_CP32_OP2_MASK (0x000e0000) 173 #define HSR_CP32_OP2_SHIFT (17) 174 #define HSR_CP32_OP1_MASK (0x0001c000) 175 #define HSR_CP32_OP1_SHIFT (14) 176 #define HSR_CP32_CRN_MASK (0x00003c00) 177 #define HSR_CP32_CRN_SHIFT (10) 178 #define HSR_CP32_CRM_MASK (0x0000001e) 179 #define HSR_CP32_CRM_SHIFT (1) 180 #define HSR_CP32_REGS_MASK (HSR_CP32_OP1_MASK|HSR_CP32_OP2_MASK|\ 181 HSR_CP32_CRN_MASK|HSR_CP32_CRM_MASK) 182 183 /* HSR.EC == HSR_CP{15,14}_64 */ 184 #define HSR_CP64_OP1_MASK (0x000f0000) 185 #define HSR_CP64_OP1_SHIFT (16) 186 #define HSR_CP64_CRM_MASK (0x0000001e) 187 #define HSR_CP64_CRM_SHIFT (1) 188 #define HSR_CP64_REGS_MASK (HSR_CP64_OP1_MASK|HSR_CP64_CRM_MASK) 189 190 /* HSR.EC == HSR_SYSREG */ 191 #define HSR_SYSREG_OP0_MASK (0x00300000) 192 #define HSR_SYSREG_OP0_SHIFT (20) 193 #define HSR_SYSREG_OP1_MASK (0x0001c000) 194 #define HSR_SYSREG_OP1_SHIFT (14) 195 #define HSR_SYSREG_CRN_MASK (0x00003c00) 196 #define HSR_SYSREG_CRN_SHIFT (10) 197 #define HSR_SYSREG_CRM_MASK (0x0000001e) 198 #define HSR_SYSREG_CRM_SHIFT (1) 199 #define HSR_SYSREG_OP2_MASK (0x000e0000) 200 #define HSR_SYSREG_OP2_SHIFT (17) 201 #define HSR_SYSREG_REGS_MASK (HSR_SYSREG_OP0_MASK|HSR_SYSREG_OP1_MASK|\ 202 HSR_SYSREG_CRN_MASK|HSR_SYSREG_CRM_MASK|\ 203 HSR_SYSREG_OP2_MASK) 204 205 /* HSR.EC == HSR_{HVC32, HVC64, SMC64, SVC32, SVC64} */ 206 #define HSR_XXC_IMM_MASK (0xffff) 207 208 #endif /* __ASM_ARM_HSR_H */ 209 210 /* 211 * Local variables: 212 * mode: C 213 * c-file-style: "BSD" 214 * c-basic-offset: 4 215 * indent-tabs-mode: nil 216 * End: 217 */ 218