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Searched refs:processor (Results 1 – 25 of 56) sorted by relevance

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/xen/xen/arch/arm/
A Dprocessor.c21 static DEFINE_PER_CPU(struct processor *, processor);
31 this_cpu(processor) = procinfo->processor; in processor_setup()
36 if ( !this_cpu(processor) || !this_cpu(processor)->vcpu_initialise ) in processor_vcpu_initialise()
39 this_cpu(processor)->vcpu_initialise(v); in processor_vcpu_initialise()
A Dgic-v2.c1165 struct acpi_madt_generic_interrupt *processor = in gic_acpi_parse_madt_cpu() local
1168 if ( BAD_MADT_ENTRY(processor, end) ) in gic_acpi_parse_madt_cpu()
1174 cbase = processor->base_address; in gic_acpi_parse_madt_cpu()
1176 hbase = processor->gich_base_address; in gic_acpi_parse_madt_cpu()
1177 vbase = processor->gicv_base_address; in gic_acpi_parse_madt_cpu()
1178 gicv2_info.maintenance_irq = processor->vgic_interrupt; in gic_acpi_parse_madt_cpu()
1180 if ( processor->flags & ACPI_MADT_VGIC_IRQ_MODE ) in gic_acpi_parse_madt_cpu()
1189 if ( cbase != processor->base_address in gic_acpi_parse_madt_cpu()
1190 || hbase != processor->gich_base_address in gic_acpi_parse_madt_cpu()
1191 || vbase != processor->gicv_base_address in gic_acpi_parse_madt_cpu()
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A Dvtimer.c108 init_timer(&t->timer, phys_timer_expired, t, v->processor); in vcpu_vtimer_init()
116 init_timer(&t->timer, virt_timer_expired, t, v->processor); in vcpu_vtimer_init()
157 migrate_timer(&v->arch.virt_timer.timer, v->processor); in virt_timer_restore()
158 migrate_timer(&v->arch.phys_timer.timer, v->processor); in virt_timer_restore()
A Dgic-v3.c1558 struct acpi_madt_generic_interrupt *processor = in gic_acpi_parse_madt_cpu() local
1561 if ( BAD_MADT_ENTRY(processor, end) ) in gic_acpi_parse_madt_cpu()
1567 cbase = processor->base_address; in gic_acpi_parse_madt_cpu()
1568 vbase = processor->gicv_base_address; in gic_acpi_parse_madt_cpu()
1569 gicv3_info.maintenance_irq = processor->vgic_interrupt; in gic_acpi_parse_madt_cpu()
1571 if ( processor->flags & ACPI_MADT_VGIC_IRQ_MODE ) in gic_acpi_parse_madt_cpu()
1580 if ( cbase != processor->base_address in gic_acpi_parse_madt_cpu()
1581 || vbase != processor->gicv_base_address in gic_acpi_parse_madt_cpu()
1611 struct acpi_madt_generic_interrupt *processor; in gic_acpi_parse_cpu_redistributor() local
1614 processor = (struct acpi_madt_generic_interrupt *)header; in gic_acpi_parse_cpu_redistributor()
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A DKconfig153 If a Cortex-A53 processor is executing a store or prefetch for
154 write instruction at the same time as a processor in another
176 If the processor is executing a load and store exclusive sequence at
177 the same time as a processor in another cluster is executing a cache
A Dvgic.c285 irq_set_affinity(p->desc, cpumask_of(new->processor)); in vgic_migrate_irq()
293 irq_set_affinity(p->desc, cpumask_of(new->processor)); in vgic_migrate_irq()
309 const cpumask_t *cpu_mask = cpumask_of(v->processor); in arch_move_irqs()
410 irq_set_affinity(p->desc, cpumask_of(v_target->processor)); in vgic_enable_irqs()
A DMakefile41 obj-y += processor.o
A DKconfig.debug136 bool "Early printk with SCIF0 on Renesas Lager board (R-Car H2 processor)"
152 bool "Early printk with pl011 for AMD Seattle processor"
161 bool "Early printk with pl011 for Cavium ThunderX processor"
/xen/xen/arch/x86/acpi/
A Dboot.c85 struct acpi_madt_local_x2apic *processor = in acpi_parse_x2apic() local
89 if (BAD_MADT_ENTRY(processor, end)) in acpi_parse_x2apic()
99 if (processor->local_apic_id >= MAX_APICS || in acpi_parse_x2apic()
100 processor->uid >= MAX_MADT_ENTRIES) { in acpi_parse_x2apic()
106 processor->local_apic_id, processor->uid); in acpi_parse_x2apic()
115 x86_acpiid_to_apicid[processor->uid] = in acpi_parse_x2apic()
116 processor->local_apic_id; in acpi_parse_x2apic()
135 struct acpi_madt_local_apic *processor = in acpi_parse_lapic() local
139 if (BAD_MADT_ENTRY(processor, end)) in acpi_parse_lapic()
143 processor->id != 0xff || opt_cpu_info) in acpi_parse_lapic()
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/xen/xen/arch/arm/acpi/
A Dboot.c52 acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) in acpi_map_gic_cpu_interface() argument
56 u64 mpidr = processor->arm_mpidr & MPIDR_HWID_MASK; in acpi_map_gic_cpu_interface()
57 bool enabled = processor->flags & ACPI_MADT_ENABLED; in acpi_map_gic_cpu_interface()
131 struct acpi_madt_generic_interrupt *processor = in acpi_parse_gic_cpu_interface() local
134 if ( BAD_MADT_ENTRY(processor, end) ) in acpi_parse_gic_cpu_interface()
138 acpi_map_gic_cpu_interface(processor); in acpi_parse_gic_cpu_interface()
/xen/xen/include/asm-arm/
A Dprocinfo.h26 struct processor { struct
35 struct processor *processor; argument
/xen/xen/arch/x86/
A Dmpparse.c495 struct mpc_config_processor processor; in construct_default_ISA_mptable() local
510 processor.mpc_type = MP_PROCESSOR; in construct_default_ISA_mptable()
513 processor.mpc_cpuflag = CPU_ENABLED; in construct_default_ISA_mptable()
514 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | in construct_default_ISA_mptable()
517 processor.mpc_featureflag = in construct_default_ISA_mptable()
519 processor.mpc_reserved[0] = 0; in construct_default_ISA_mptable()
520 processor.mpc_reserved[1] = 0; in construct_default_ISA_mptable()
522 processor.mpc_apicid = i; in construct_default_ISA_mptable()
523 MP_processor_info(&processor); in construct_default_ISA_mptable()
800 struct mpc_config_processor processor = { in mp_register_lapic() local
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/xen/tools/libacpi/
A Dbuild.c218 struct acpi_20_srat_processor *processor; in construct_srat() local
224 size = sizeof(*srat) + sizeof(*processor) * config->hvminfo->nr_vcpus + in construct_srat()
241 processor = (struct acpi_20_srat_processor *)(srat + 1); in construct_srat()
244 processor->type = ACPI_PROCESSOR_AFFINITY; in construct_srat()
245 processor->length = sizeof(*processor); in construct_srat()
246 processor->domain = config->numa.vcpu_to_vnode[i]; in construct_srat()
247 processor->apic_id = config->lapic_id(i); in construct_srat()
248 processor->flags = ACPI_LOCAL_APIC_AFFIN_ENABLED; in construct_srat()
249 processor++; in construct_srat()
252 memory = (struct acpi_20_srat_memory *)processor; in construct_srat()
/xen/xen/common/sched/
A Dcore.c248 atomic_dec(&per_cpu(sched_urgent_count, v->processor)); in vcpu_urgent_count_update()
538 unsigned int processor; in sched_init_vcpu() local
544 processor = v->vcpu_id; in sched_init_vcpu()
546 processor = sched_select_initial_cpu(v); in sched_init_vcpu()
552 init_timer(&v->poll_timer, poll_timer_fn, v, processor); in sched_init_vcpu()
557 v->processor = processor; in sched_init_vcpu()
564 sched_set_res(unit, get_sched_res(processor)); in sched_init_vcpu()
586 get_sched_res(v->processor)->curr = unit; in sched_init_vcpu()
587 get_sched_res(v->processor)->sched_unit_idle = unit; in sched_init_vcpu()
743 atomic_dec(&per_cpu(sched_urgent_count, v->processor)); in sched_destroy_vcpu()
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/xen/xen/arch/arm/arm32/
A Dproc-caxx.c33 const struct processor caxx_processor = {
/xen/xen/include/xen/
A Dnuma.h15 #define vcpu_to_node(v) (cpu_to_node((v)->processor))
/xen/docs/misc/
A Damd-ucode-container.txt16 processor families 10h, 11h, 12h, 14h, and 15h.
19 * For AMD processor families 15h and later, there is a separate container file
22 sure you have the latest container file for your AMD processor family.
A Dvtd-pi.txt20 processed by processor or software) for this Posted Interrupt Descriptor. When this field is 0,
22 the notification event (processor or software) resets it as part of posted interrupt processing.
31 processor for the notification event.
91 Posted-interrupt processing is a feature by which a processor processes
98 In response to such an interrupt, the processor processes virtual interrupts
/xen/docs/admin-guide/
A Dmicrocode-loading.rst8 can be considered as firmware for the processor, and updates are published as
20 Microcode can make almost arbitrary changes to the processor, including to
46 processor : 0
62 also the format which the processor accepts. This format contains header
137 correct for the processor, and newer than the running microcode.
/xen/docs/man/
A Dxen-tscmode.7.pod32 per second per processor, we call this a "high-TSC-frequency"
123 processor that increases monotonically. Historically, TSC incremented
124 every processor cycle, but on recent processors, it increases
125 at a constant rate even if the processor changes frequency (for example,
126 to reduce processor power usage). TSC is known by x86 programmers
137 one processor, then was moved by the OS to another processor, then read
145 machines, the TSC was synchronized but if one processor were to enter
198 per second per processor), this performance degradation is not noticeable
/xen/xen/common/
A Dkeyhandler.c216 tasklet_schedule_on_cpu(&dump_hwdom_tasklet, v->processor); in dump_hwdom_action()
237 tasklet_schedule_on_cpu(&dump_hwdom_tasklet, v->processor); in dump_hwdom_registers()
314 v->vcpu_id, v->processor, in dump_domains()
/xen/xen/arch/x86/hvm/
A Dvpt.c481 migrate_timer(&pt->timer, v->processor); in pt_migrate()
549 init_timer(&pt->timer, pt_timer_fn, pt, v->processor); in create_periodic_time()
588 migrate_timer(&pt->timer, v->processor); in pt_adjust_vcpu()
/xen/docs/features/
A Dintel_psr_cat_cdp.pandoc39 configured, the processor allows access to portions of cache according to the
40 established COS. Intel Xeon processor E5 v4 family (and some others) introduce
42 Intel Goldmont processor provides support for control over the L2 cache.
180 HW may support all features. By default, CDP is disabled on the processor.
181 If the L3 CAT MSRs are used without enabling CDP, the processor operates in
/xen/xen/arch/x86/hvm/viridian/
A Dtime.c209 migrate_timer(&vs->timer, v->processor); in start_stimer()
507 init_timer(&vs->timer, stimer_expire, vs, v->processor); in viridian_time_vcpu_init()
/xen/docs/misc/arm/
A Dsilicon-errata.txt21 of code, or configuring the processor in a particular way. A less common

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