Searched defs:pll_info (Results 1 – 10 of 10) sorted by relevance
85 const struct ingenic_cgu_pll_info *pll_info; in ingenic_pll_recalc_rate() local123 ingenic_pll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, in ingenic_pll_calc_m_n_od()151 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_calc() local181 const struct ingenic_cgu_pll_info *pll_info) in ingenic_pll_check_stable()197 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_set_rate() local237 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_enable() local268 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_disable() local286 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_is_enabled() local
57 jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, in jz4760_cgu_calc_m_n_od()
123 struct pll_info { struct133 unsigned long target, struct pll_info *pll, in rcar_lvds_d3_e3_pll_calc() argument
47 struct pll_info { struct48 int pll_max;49 int pll_min;50 int sclk, mclk, mclk_pm, xclk;51 int ref_div;52 int ref_clk;53 int ecp_max;
138 struct pll_info { struct139 int ppll_max;140 int ppll_min;141 int sclk, mclk;142 int ref_div;143 int ref_clk;
763 const struct audio_pll_info *pll_info, in get_azalia_clock_info_dp()785 const struct audio_pll_info *pll_info) in dce_aud_wall_dto_setup()877 const struct audio_pll_info *pll_info) in dce60_aud_wall_dto_setup()
159 struct pll_info { struct160 uint32_t crystal_frequency; /* in KHz */161 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */162 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */163 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */164 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */165 } pll_info; member
99 struct audio_pll_info pll_info; member
62 static const struct ccu_pll_info pll_info[] = { variable
732 uint16_t pll_info; in radeon_combios_get_clock_info() local
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