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Searched defs:reg_name (Results 26 – 50 of 218) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
A Dhw_translate_dcn30.c61 #define REG(reg_name)\ argument
63 #define SF_HPD(reg_name, field_name, post_fix)\ argument
/linux/drivers/crypto/ux500/cryp/
A Dcryp_p.h23 #define CRYP_SET_BITS(reg_name, mask) \ argument
26 #define CRYP_WRITE_BIT(reg_name, val, mask) \ argument
30 #define CRYP_TEST_BITS(reg_name, val) \ argument
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_hubbub.c40 #define FN(reg_name, field_name) \ argument
50 #define FN(reg_name, field_name) \ argument
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce60/
A Dhw_factory_dce60.c41 #define REG(reg_name)\ argument
83 #define SF_DDC(reg_name, field_name, post_fix)\ argument
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce80/
A Dhw_factory_dce80.c41 #define REG(reg_name)\ argument
83 #define SF_DDC(reg_name, field_name, post_fix)\ argument
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c246 #define SR(reg_name)\ argument
250 #define SRI(reg_name, block, id)\ argument
254 #define SRI2(reg_name, block, id)\ argument
262 #define SRII(reg_name, block, id)\ argument
266 #define SRII_MPC_RMU(reg_name, block, id)\ argument
274 #define DCCG_SRII(reg_name, block, id)\ argument
278 #define VUPDATE_SRII(reg_name, block, id)\ argument
289 #define NBIO_SR(reg_name)\ argument
300 #define MMHUB_SR(reg_name)\ argument
311 #define CLK_SRI(reg_name, block, inst)\ argument
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/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_link_encoder.c49 #define FN(reg_name, field_name) \ argument
1367 #define HPD_REG_READ(reg_name) \ argument
1370 #define HPD_REG_UPDATE_N(reg_name, n, ...) \ argument
1375 #define HPD_REG_UPDATE(reg_name, field, val) \ argument
1398 #define AUX_REG_READ(reg_name) \ argument
1401 #define AUX_REG_UPDATE_N(reg_name, n, ...) \ argument
1406 #define AUX_REG_UPDATE(reg_name, field, val) \ argument
A Ddcn10_resource.c172 #define SR(reg_name)\ argument
176 #define SRI(reg_name, block, id)\ argument
181 #define SRII(reg_name, block, id)\ argument
185 #define VUPDATE_SRII(reg_name, block, id)\ argument
190 #define SFRB(field_name, reg_name, bitfield, post_fix)\ argument
200 #define NBIO_SR(reg_name)\ argument
211 #define MMHUB_SR(reg_name)\ argument
A Ddcn10_dpp.h37 #define TF_SF(reg_name, field_name, post_fix)\ argument
41 #define TF2_SF(reg_name, field_name, post_fix)\ argument
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
A Ddce60_clk_mgr.c50 #define FN(reg_name, field_name) \ argument
54 #define SR(reg_name)\ argument
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_link_encoder.c46 #define FN(reg_name, field_name) \ argument
304 #define AUX_REG_READ(reg_name) \ argument
307 #define AUX_REG_WRITE(reg_name, val) \ argument
A Ddcn20_dccg.h51 #define DCCG_SF(reg_name, field_name, post_fix)\ argument
54 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ argument
57 #define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ argument
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c326 #define SR(reg_name)\ argument
330 #define SRI(reg_name, block, id)\ argument
334 #define SRIR(var_name, reg_name, block, id)\ argument
338 #define SRII(reg_name, block, id)\ argument
342 #define DCCG_SRII(reg_name, block, id)\ argument
346 #define VUPDATE_SRII(reg_name, block, id)\ argument
357 #define NBIO_SR(reg_name)\ argument
368 #define MMHUB_SR(reg_name)\ argument
1891 #define REG(reg_name) \ argument
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_dio_link_encoder.c51 #define FN(reg_name, field_name) \ argument
60 #define AUX_REG_READ(reg_name) \ argument
63 #define AUX_REG_WRITE(reg_name, val) \ argument
/linux/drivers/staging/media/hantro/
A Dhantro_postproc.c15 #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ argument
22 #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \ argument
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
A Ddce112_clk_mgr.c37 #define SR(reg_name)\ argument
41 #define SRI(reg_name, block, id)\ argument
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c54 #define FN(reg_name, field_name) \ argument
64 #define SR(reg_name)\ argument
69 #define CLK_SRI(reg_name, block, inst)\ argument
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
A Ddce110_clk_mgr.c35 #define SR(reg_name)\ argument
39 #define SRI(reg_name, block, id)\ argument
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
A Drv1_clk_mgr_vbios_smu.c63 #define REG(reg_name) \ argument
66 #define FN(reg_name, field) \ argument
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
A Ddcn201_clk_mgr.c49 #define SR(reg_name)\ argument
57 #define FN(reg_name, field_name) \ argument
/linux/scripts/
A Dmarkup_oops.pl86 sub reg_name subroutine
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_hwseq.c39 #define FN(reg_name, field_name) \ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c214 #define SRI(reg_name, block, id)\ argument
218 #define SRI_DMUB(reg_name)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c187 #define SRI(reg_name, block, id)\ argument
191 #define SRI_DMUB(reg_name)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c201 #define SRI(reg_name, block, id)\ argument
205 #define SRI_DMUB(reg_name)\ argument

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