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Searched defs:unit (Results 1 – 14 of 14) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dxor_regs.h17 #define MV_XOR_REGS_OFFSET(unit) (0xF0800) argument
19 #define MV_XOR_REGS_OFFSET(unit) (0x60900) argument
21 #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) argument
24 #define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit)) argument
29 #define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x30) argument
30 #define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x40) argument
31 #define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x50) argument
32 #define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x60) argument
41 #define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D0) argument
44 #define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E0) argument
[all …]
A Dddr3_axp.h424 #define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit)) argument
/u-boot/drivers/ddr/marvell/a38x/
A Dxor_regs.h16 #define MV_XOR_REGS_OFFSET(unit) (0x60900) argument
17 #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) argument
20 #define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit)) argument
21 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
23 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
27 #define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x30)) argument
28 #define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x40)) argument
29 #define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x50)) argument
30 #define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x60)) argument
41 #define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
[all …]
A Dmv_ddr_sys_env_lib.h21 #define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40)) argument
/u-boot/cmd/
A Dclone.c20 char *unit, *buf; in do_clone() local
/u-boot/arch/arm/mach-mvebu/serdes/a38x/
A Dsys_env_lib.c157 u32 sys_env_unit_max_num_get(enum unit_id unit) in sys_env_unit_max_num_get()
A Dsys_env_lib.h244 #define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40)) argument
/u-boot/scripts/dtc/
A Ddtc.c47 const char *unit; in fill_fullpaths() local
/u-boot/arch/arm/mach-mvebu/serdes/axp/
A Dboard_env_spec.h95 #define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x40)) argument
97 #define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit)) argument
127 #define PEX_PHY_ACCESS_REG(unit) (0x40000 + ((unit) % 2 * 0x40000) + \ argument
/u-boot/drivers/video/
A Divybridge_igd.c320 u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf; in gma_pm_init_pre_vbios() local
/u-boot/arch/x86/cpu/quark/
A Dmrc_util.c32 void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask) in mrc_write_mask()
39 void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask) in mrc_alt_write_mask()
/u-boot/include/power/
A Dtps65910_pmic.h121 uint unit; /* unit-address according to DT */ member
/u-boot/drivers/phy/marvell/
A Dcomphy_a3700.h78 static inline void __iomem *phy_addr(enum phy_unit unit, u32 addr) in phy_addr()
/u-boot/drivers/ram/stm32mp1/
A Dstm32mp1_tuning.c57 u8 unit; /* DQS unit delay */ member

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