Searched refs:BIT10 (Results 1 – 17 of 17) sorted by relevance
| /linux/drivers/staging/rtl8723bs/include/ |
| A D | hal_com_reg.h | 618 #define RRSR_48M BIT10
766 #define IMR_ATIMEND BIT10 /* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it al…
782 #define IMR_RXERR BIT10
814 #define PHIMR_C2HCMD BIT10
837 #define PHIMR_RXERR BIT10
865 #define UHIMR_C2HCMD BIT10
890 #define UHIMR_RXERR BIT10
919 #define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */
948 #define IMR_RXERR_88E BIT10 /* Rx Error Flag INT Status, Write 1 clear */
1013 #define RCR_RSVD_BIT10 BIT10 /* Reserved */
|
| A D | rtl8723b_spec.h | 204 #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */
233 #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */
|
| A D | osdep_service.h | 27 #define BIT10 0x00000400 macro
|
| A D | rtw_mlme_ext.h | 54 #define DYNAMIC_BB_PATH_DIV BIT10/* ODM_BB_PATH_DIV */
|
| /linux/drivers/staging/rtl8723bs/hal/ |
| A D | rtl8723b_rf6052.c | 65 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11); in PHY_RF6052SetBandwidth8723B()
71 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10); in PHY_RF6052SetBandwidth8723B()
|
| A D | Hal8723BReg.h | 393 #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */
422 #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */
|
| A D | odm.h | 376 ODM_BB_PATH_DIV = BIT10,
|
| A D | odm_DIG.c | 22 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
|
| /linux/drivers/staging/rtl8192e/rtl8192e/ |
| A D | r8192E_hw.h | 218 #define IMR_RXCMDOK BIT10
241 #define TPPoll_StopBE BIT10
371 #define RRSR_48M BIT10
|
| /linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| A D | halbt_precomp.h | 41 #define BIT10 0x00000400 macro
|
| /linux/drivers/staging/rtl8192e/ |
| A D | rtl819x_Qos.h | 20 #define BIT10 0x00000400 macro
|
| /linux/include/uapi/linux/ |
| A D | synclink.h | 29 #define BIT10 0x0400 macro
|
| /linux/drivers/scsi/ |
| A D | dc395x.h | 66 #define BIT10 0x00000400 macro
|
| /linux/drivers/tty/ |
| A D | synclink_gt.c | 389 #define IRQ_RXDATA BIT10
2047 if (count == info->rbuf_fill_level || (reg & BIT10)) { in isr_rxdata()
4206 case HDLC_ENCODING_NRZB: val |= BIT10; break; in sync_mode()
4208 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()
4210 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()
4212 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
4279 case HDLC_ENCODING_NRZB: val |= BIT10; break; in sync_mode()
4281 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()
4283 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()
4285 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
|
| /linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/ |
| A D | reg.h | 368 #define RRSR_48M BIT10
|
| /linux/drivers/scsi/lpfc/ |
| A D | lpfc_hw4.h | 742 #define LPFC_SLI4_INTR10 BIT10
|
| /linux/drivers/char/pcmcia/ |
| A D | synclink_cs.c | 295 #define IRQ_CTS BIT10 // CTS status change
|
Completed in 79 milliseconds