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Searched refs:CLEAR0 (Results 1 – 2 of 2) sorted by relevance

/linux/arch/mips/loongson64/
A Dsmp.c240 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0); in ipi_clear0_regs_init()
242 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0); in ipi_clear0_regs_init()
244 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0); in ipi_clear0_regs_init()
246 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0); in ipi_clear0_regs_init()
248 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0); in ipi_clear0_regs_init()
250 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0); in ipi_clear0_regs_init()
252 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0); in ipi_clear0_regs_init()
254 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0); in ipi_clear0_regs_init()
256 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0); in ipi_clear0_regs_init()
258 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0); in ipi_clear0_regs_init()
[all …]
A Dsmp.h24 #define CLEAR0 0x0c macro

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