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Searched refs:CLK_ENABLE_ON_INIT (Results 1 – 22 of 22) sorted by relevance

/linux/arch/sh/kernel/cpu/sh4a/
A Dclock-sh7366.c59 .flags = CLK_ENABLE_ON_INIT,
81 .flags = CLK_ENABLE_ON_INIT,
112 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
113 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
114 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
115 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
116 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
142 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
143 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
174 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
[all …]
A Dclock-sh7723.c63 .flags = CLK_ENABLE_ON_INIT,
85 .flags = CLK_ENABLE_ON_INIT,
115 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
116 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
117 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
118 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
119 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
143 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
144 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
145 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
[all …]
A Dclock-sh7343.c59 .flags = CLK_ENABLE_ON_INIT,
78 .flags = CLK_ENABLE_ON_INIT,
109 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
110 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
111 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
112 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
113 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
139 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
140 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
141 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
[all …]
A Dclock-sh7724.c68 .flags = CLK_ENABLE_ON_INIT,
87 .flags = CLK_ENABLE_ON_INIT,
154 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
155 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
156 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
158 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
194 [DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT,
203 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
204 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
205 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
[all …]
A Dclock-sh7722.c62 .flags = CLK_ENABLE_ON_INIT,
84 .flags = CLK_ENABLE_ON_INIT,
114 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
115 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
116 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
117 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
118 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
142 [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
143 [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
A Dclock-sh7785.c43 .flags = CLK_ENABLE_ON_INIT,
73 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
74 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
75 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
76 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
77 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
A Dclock-shx3.c39 .flags = CLK_ENABLE_ON_INIT,
67 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
68 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
69 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
70 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
A Dclock-sh7734.c45 .flags = CLK_ENABLE_ON_INIT,
73 [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
74 [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
75 [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
76 [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
77 [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
78 [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
A Dclock-sh7757.c40 .flags = CLK_ENABLE_ON_INIT,
70 [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
71 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
72 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
A Dclock-sh7786.c45 .flags = CLK_ENABLE_ON_INIT,
73 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
74 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
75 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
76 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
A Dclock-sh7763.c79 .flags = CLK_ENABLE_ON_INIT,
A Dclock-sh7780.c85 .flags = CLK_ENABLE_ON_INIT,
/linux/arch/sh/kernel/cpu/
A Dclock-cpg.c10 .flags = CLK_ENABLE_ON_INIT,
16 .flags = CLK_ENABLE_ON_INIT,
21 .flags = CLK_ENABLE_ON_INIT,
26 .flags = CLK_ENABLE_ON_INIT,
/linux/arch/sh/kernel/cpu/sh2a/
A Dclock-sh7269.c50 .flags = CLK_ENABLE_ON_INIT,
65 .flags = CLK_ENABLE_ON_INIT,
80 .flags = CLK_ENABLE_ON_INIT,
111 | CLK_ENABLE_ON_INIT),
113 | CLK_ENABLE_ON_INIT),
A Dclock-sh7264.c54 .flags = CLK_ENABLE_ON_INIT,
83 | CLK_ENABLE_ON_INIT),
/linux/drivers/clk/renesas/
A Dclk-r8a7740.c30 #define CLK_ENABLE_ON_INIT BIT(0) macro
40 { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
41 { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
42 { "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
43 { "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
A Dclk-r8a73a4.c34 #define CLK_ENABLE_ON_INIT BIT(0) macro
A Dclk-sh73a0.c38 #define CLK_ENABLE_ON_INIT BIT(0) macro
/linux/arch/sh/kernel/cpu/sh4/
A Dclock-sh4-202.c46 .flags = CLK_ENABLE_ON_INIT,
61 .flags = CLK_ENABLE_ON_INIT,
137 .flags = CLK_ENABLE_ON_INIT,
/linux/include/linux/
A Dsh_clk.h68 #define CLK_ENABLE_ON_INIT BIT(0) macro
/linux/drivers/sh/clk/
A Dcpg.c347 if (parent->flags & CLK_ENABLE_ON_INIT) in sh_clk_div4_set_parent()
A Dcore.c467 if (clkp->flags & CLK_ENABLE_ON_INIT) in clk_enable_init_clocks()

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