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Searched refs:CLK_SMMU_MDMA0 (Results 1 – 4 of 4) sorted by relevance

/linux/include/dt-bindings/clock/
A Dexynos5250.h150 #define CLK_SMMU_MDMA0 347 macro
A Dexynos5420.h185 #define CLK_SMMU_MDMA0 504 macro
/linux/drivers/clk/samsung/
A Dclk-exynos5250.c447 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
A Dclk-exynos5420.c932 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),

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