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Searched refs:CLK_TOP_A1SYS_HP_SEL (Results 1 – 7 of 7) sorted by relevance

/linux/include/dt-bindings/clock/
A Dmt7622-clk.h82 #define CLK_TOP_A1SYS_HP_SEL 70 macro
A Dmt2712-clk.h172 #define CLK_TOP_A1SYS_HP_SEL 141 macro
/linux/Documentation/devicetree/bindings/sound/
A Dmt8195-afe-pcm.yaml150 <&topckgen 100>, //CLK_TOP_A1SYS_HP_SEL
/linux/drivers/clk/mediatek/
A Dclk-mt7622.c549 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
A Dclk-mt2712.c832 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
/linux/arch/arm64/boot/dts/mediatek/
A Dmt7622.dtsi672 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
A Dmt2712e.dtsi289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,

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