Searched refs:CLK_TOP_APLL12_DIV5 (Results 1 – 10 of 10) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | mt8516-clk.h | 157 #define CLK_TOP_APLL12_DIV5 125 macro
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| A D | mt6779-clk.h | 144 #define CLK_TOP_APLL12_DIV5 134 macro
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| A D | mt8192-clk.h | 160 #define CLK_TOP_APLL12_DIV5 148 macro
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| /linux/sound/soc/mediatek/mt8192/ |
| A D | mt8192-afe-clk.h | 212 CLK_TOP_APLL12_DIV5, enumerator
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| A D | mt8192-afe-clk.c | 55 [CLK_TOP_APLL12_DIV5] = "top_apll12_div5",
501 .div_clk_id = CLK_TOP_APLL12_DIV5,
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt8516.c | 672 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
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| A D | clk-mt8167.c | 918 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
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| A D | clk-mt6779.c | 840 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
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| A D | clk-mt8192.c | 867 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16),
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt8183.dtsi | 1169 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
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