Searched refs:CLK_TOP_AXI_SEL (Results 1 – 20 of 20) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | mt8135-clk.h | 73 #define CLK_TOP_AXI_SEL 62 macro
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| A D | mt7629-clk.h | 83 #define CLK_TOP_AXI_SEL 73 macro
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| A D | mt7622-clk.h | 68 #define CLK_TOP_AXI_SEL 56 macro
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| A D | mt6765-clk.h | 131 #define CLK_TOP_AXI_SEL 96 macro
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| A D | mt8173-clk.h | 92 #define CLK_TOP_AXI_SEL 82 macro
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| A D | mt2712-clk.h | 130 #define CLK_TOP_AXI_SEL 99 macro
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| A D | mt2701-clk.h | 90 #define CLK_TOP_AXI_SEL 79 macro
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| A D | mt8192-clk.h | 12 #define CLK_TOP_AXI_SEL 0 macro
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| /linux/arch/arm/boot/dts/ |
| A D | mt7629.dtsi | 268 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
320 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
389 <&topckgen CLK_TOP_AXI_SEL>,
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt7629.c | 487 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
593 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); in mtk_topckgen_init()
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| A D | clk-mt7622.c | 515 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
639 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); in mtk_topckgen_init()
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| A D | clk-mt8135.c | 352 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| A D | clk-mt2701.c | 488 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| A D | clk-mt8173.c | 542 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
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| A D | clk-mt8192.c | 708 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
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| A D | clk-mt2712.c | 738 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
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| A D | clk-mt6765.c | 367 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt7622.dtsi | 252 <&topckgen CLK_TOP_AXI_SEL>;
699 <&topckgen CLK_TOP_AXI_SEL>;
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| A D | mt2712e.dtsi | 774 <&topckgen CLK_TOP_AXI_SEL>,
785 <&topckgen CLK_TOP_AXI_SEL>,
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| A D | mt8173.dtsi | 894 <&topckgen CLK_TOP_AXI_SEL>;
904 <&topckgen CLK_TOP_AXI_SEL>;
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