Searched refs:CLK_TOP_UNIVPLL1_D8 (Results 1 – 16 of 16) sorted by relevance
| /linux/Documentation/devicetree/bindings/spi/ |
| A D | spi-slave-mt27xx.txt | 21 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
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| A D | spi-mt65xx.txt | 35 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
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| /linux/include/dt-bindings/clock/ |
| A D | mt8135-clk.h | 46 #define CLK_TOP_UNIVPLL1_D8 35 macro
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| A D | mt7629-clk.h | 52 #define CLK_TOP_UNIVPLL1_D8 42 macro
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| A D | mt7622-clk.h | 46 #define CLK_TOP_UNIVPLL1_D8 34 macro
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| A D | mt6797-clk.h | 70 #define CLK_TOP_UNIVPLL1_D8 60 macro
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| A D | mt8173-clk.h | 75 #define CLK_TOP_UNIVPLL1_D8 65 macro
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| A D | mt2712-clk.h | 59 #define CLK_TOP_UNIVPLL1_D8 28 macro
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| A D | mt2701-clk.h | 38 #define CLK_TOP_UNIVPLL1_D8 28 macro
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt8135.c | 64 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
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| A D | clk-mt7629.c | 420 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
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| A D | clk-mt6797.c | 51 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
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| A D | clk-mt7622.c | 412 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
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| A D | clk-mt2701.c | 86 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
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| A D | clk-mt8173.c | 110 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
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| A D | clk-mt2712.c | 102 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
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