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Searched refs:CNVC_SURFACE_PIXEL_FORMAT (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_ipp.h36 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
80 IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
147 type CNVC_SURFACE_PIXEL_FORMAT; \
185 uint32_t CNVC_SURFACE_PIXEL_FORMAT; member
A Ddcn10_dpp.c388 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp1_cnv_setup()
389 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); in dpp1_cnv_setup()
A Ddcn10_dpp_cm.c710 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp1_full_bypass()
711 CNVC_SURFACE_PIXEL_FORMAT, 0x8); in dpp1_full_bypass()
A Ddcn10_dpp.h120 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
326 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
1071 type CNVC_SURFACE_PIXEL_FORMAT; \
1339 uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_dpp.c163 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp201_cnv_setup()
164 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); in dpp201_cnv_setup()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dpp.c222 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp2_cnv_setup()
223 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); in dpp2_cnv_setup()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dpp.h135 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
299 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
A Ddcn30_dpp.c305 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp3_cnv_setup()
306 CNVC_SURFACE_PIXEL_FORMAT, pixel_format, in dpp3_cnv_setup()

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