Searched refs:DCLK (Results 1 – 15 of 15) sorted by relevance
| /linux/drivers/gpu/drm/amd/pm/inc/ |
| A D | power_state.h | 144 uint32_t DCLK; member
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| /linux/drivers/gpu/drm/i915/gt/ |
| A D | intel_llc.c | 62 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf; in get_ia_constants()
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | st,nomadik.txt | 99 58: 3DCLK
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| /linux/arch/arm/boot/dts/ |
| A D | imx6dl-eckelmann-ci4x10.dts | 220 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | processpptables.c | 759 ps->uvd_clocks.DCLK = le32_to_cpu(pnon_clock_info->ulDCLK); in init_non_clock_fields()
762 ps->uvd_clocks.DCLK = 0; in init_non_clock_fields()
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| A D | smu10_hwmgr.c | 924 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu10_dpm_get_pp_table_entry()
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| A D | smu8_hwmgr.c | 1416 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu8_dpm_get_pp_table_entry()
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| A D | smu7_hwmgr.c | 3597 power_state->uvd_clocks.DCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3690 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v1()
3838 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v0()
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| A D | vega10_hwmgr.c | 3144 power_state->uvd_clocks.DCLK = 0; in vega10_get_pp_table_entry_callback_func()
3224 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in vega10_get_pp_table_entry()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| A D | renoir_ppt.c | 113 CLK_MAP(DCLK, CLOCK_DCLK),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | aldebaran_ppt.c | 147 CLK_MAP(DCLK, PPCLK_DCLK),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | arcturus_ppt.c | 173 CLK_MAP(DCLK, PPCLK_DCLK),
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| A D | navi10_ppt.c | 157 CLK_MAP(DCLK, PPCLK_DCLK),
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| A D | sienna_cichlid_ppt.c | 157 CLK_MAP(DCLK, PPCLK_DCLK_0),
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| /linux/drivers/gpu/drm/i915/ |
| A D | i915_reg.h | 3844 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) macro
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