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Searched refs:DIV4 (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/video/fbdev/
A Dplatinumfb.h70 #define DIV4 0x40 macro
169 {{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }}
181 {{ 122, 7 + DIV4 }, { 62, 9 + DIV2 }}
193 {{ 26, 0 + DIV4 }, { 42, 6 + DIV2 }}
205 {{ 54, 3 + DIV4 }, { 95, 1 + DIV8 }}
217 {{ 54, 3 + DIV4 }, { 88, 1 + DIV8 }}
241 {{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }}
253 {{ 99, 4 + DIV8 }, { 42, 5 + DIV4 }}
265 {{ 26, 0 + DIV8 }, { 14, 2 + DIV4 }}
/linux/arch/sh/kernel/cpu/sh4a/
A Dclock-sh7785.c66 #define DIV4(_bit, _mask, _flags) \ macro
70 [DIV4_P] = DIV4(0, 0x0f80, 0),
71 [DIV4_DU] = DIV4(4, 0x0ff0, 0),
72 [DIV4_GA] = DIV4(8, 0x0030, 0),
73 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
74 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
75 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
76 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
77 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
A Dclock-sh7722.c108 #define DIV4(_reg, _bit, _mask, _flags) \ macro
114 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
115 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
116 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
117 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
118 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
119 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
125 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
131 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
132 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
A Dclock-shx3.c61 #define DIV4(_bit, _mask, _flags) \ macro
65 [DIV4_P] = DIV4(0, 0x0f80, 0),
66 [DIV4_SHA] = DIV4(4, 0x0ff0, 0),
67 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
68 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
69 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
70 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
A Dclock-sh7723.c111 #define DIV4(_reg, _bit, _mask, _flags) \ macro
115 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
116 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
117 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
118 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
119 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
120 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
126 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
132 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
133 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
A Dclock-sh7366.c108 #define DIV4(_reg, _bit, _mask, _flags) \ macro
112 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
113 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
114 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
115 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
116 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
117 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
118 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
119 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
A Dclock-sh7786.c67 #define DIV4(_bit, _mask, _flags) \ macro
71 [DIV4_P] = DIV4(0, 0x0b40, 0),
72 [DIV4_DU] = DIV4(4, 0x0010, 0),
73 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
74 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
75 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
76 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
A Dclock-sh7343.c105 #define DIV4(_reg, _bit, _mask, _flags) \ macro
109 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
110 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
111 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
112 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
113 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
114 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
115 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
116 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
A Dclock-sh7734.c69 #define DIV4(_reg, _bit, _mask, _flags) \ macro
73 [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
74 [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
75 [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
76 [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
77 [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
78 [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
A Dclock-sh7757.c62 #define DIV4(_bit, _mask, _flags) \ macro
70 [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
71 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
72 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
A Dclock-sh7724.c150 #define DIV4(_reg, _bit, _mask, _flags) \ macro
154 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
155 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
156 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
157 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
158 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
/linux/arch/sh/kernel/cpu/sh2a/
A Dclock-sh7264.c77 #define DIV4(_reg, _bit, _mask, _flags) \ macro
82 [DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
84 [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
A Dclock-sh7269.c105 #define DIV4(_reg, _bit, _mask, _flags) \ macro
110 [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
112 [DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
A Dda8xx-cfgchip.txt29 PLL DIV4.5 divider

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