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Searched refs:GC (Results 1 – 25 of 29) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v10_0.c4559 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
4569 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
5328 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); in gfx_v10_0_rlc_stop()
6218 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, in gfx_v10_0_cp_gfx_start()
6481 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, in gfx_v10_0_cp_compute_enable()
7087 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, in gfx_v10_0_kiq_init_register()
9283 tmp = RREG32_SOC15_IP(GC, target); in gfx_v10_0_kiq_set_interrupt_state()
9286 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
9293 tmp = RREG32_SOC15_IP(GC, target); in gfx_v10_0_kiq_set_interrupt_state()
9296 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
[all …]
A Dgfx_v9_4.c132 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
136 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
140 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
144 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
176 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
696 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
700 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
931 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
935 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
944 RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL); in gfx_v9_4_reset_ras_error_count()
[all …]
A Dgfx_v9_4_2.c784 WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL, tmp); in gfx_v9_4_2_set_power_brake_sequence()
788 WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp); in gfx_v9_4_2_set_power_brake_sequence()
793 WREG32_SOC15(GC, 0, regGC_CAC_IND_DATA, tmp); in gfx_v9_4_2_set_power_brake_sequence()
896 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
900 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
904 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
908 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
929 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
1828 WREG32_SOC15_RLC_EX(reg, GC, 0, regSQ_IND_INDEX, in wave_read_ind()
1833 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
[all …]
A Dgfxhub_v1_0.c96 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); in gfxhub_v1_0_init_system_aperture_regs()
113 WREG32_SOC15_RLC(GC, 0, in gfxhub_v1_0_init_system_aperture_regs()
119 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v1_0_init_system_aperture_regs()
145 WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); in gfxhub_v1_0_init_system_aperture_regs()
177 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); in gfxhub_v1_0_init_cache_regs()
186 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); in gfxhub_v1_0_init_cache_regs()
188 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); in gfxhub_v1_0_init_cache_regs()
191 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); in gfxhub_v1_0_init_cache_regs()
365 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); in gfxhub_v1_0_gart_disable()
417 SOC15_REG_OFFSET(GC, 0, in gfxhub_v1_0_init()
[all …]
A Dgfx_v9_0.c715 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)},
2062 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
2074 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
2615 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); in gfx_v9_0_init_sq_config()
2618 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); in gfx_v9_0_init_sq_config()
3274 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); in gfx_v9_0_cp_gfx_start()
3338 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); in gfx_v9_0_cp_gfx_resume()
3348 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v9_0_cp_gfx_resume()
3365 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v9_0_cp_gfx_resume()
3402 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, in gfx_v9_0_cp_compute_enable()
[all …]
A Dgfxhub_v2_1.c159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_1_init_system_aperture_regs()
217 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_init_cache_regs()
228 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); in gfxhub_v2_1_init_cache_regs()
230 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_init_cache_regs()
233 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); in gfxhub_v2_1_init_cache_regs()
245 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); in gfxhub_v2_1_init_cache_regs()
250 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); in gfxhub_v2_1_init_cache_regs()
254 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); in gfxhub_v2_1_init_cache_regs()
400 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); in gfxhub_v2_1_gart_disable()
463 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_1_init()
[all …]
A Dgfxhub_v2_0.c157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs()
214 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_0_init_cache_regs()
225 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); in gfxhub_v2_0_init_cache_regs()
227 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_0_init_cache_regs()
230 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); in gfxhub_v2_0_init_cache_regs()
242 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); in gfxhub_v2_0_init_cache_regs()
247 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); in gfxhub_v2_0_init_cache_regs()
251 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); in gfxhub_v2_0_init_cache_regs()
380 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); in gfxhub_v2_0_gart_disable()
437 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_0_init()
[all …]
A Dsdma_v5_0.c71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
757 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, in sdma_v5_0_gfx_resume()
[all …]
A Damdgpu_amdkfd_gfx_v10_3.c99 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in program_sh_mem_settings_v10_3()
132 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in init_interrupts_v10_3()
218 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value); in hqd_load_v10_3()
262 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in hqd_load_v10_3()
264 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in hqd_load_v10_3()
266 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, in hqd_load_v10_3()
272 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, in hqd_load_v10_3()
282 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); in hqd_load_v10_3()
485 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in hqd_is_occupied_v10_3()
552 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in hqd_destroy_v10_3()
[all …]
A Dmes_v10_1.c420 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); in mes_v10_1_enable()
422 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
436 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
444 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
480 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO, in mes_v10_1_load_microcode()
482 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI, in mes_v10_1_load_microcode()
489 WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_LO, in mes_v10_1_load_microcode()
491 WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_HI, in mes_v10_1_load_microcode()
734 data = RREG32_SOC15(GC, 0, mmCP_HQD_VMID); in mes_v10_1_queue_init_register()
736 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, data); in mes_v10_1_queue_init_register()
[all …]
A Damdgpu_amdkfd_gfx_v10.c100 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
164 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in kgd_init_interrupts()
277 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in kgd_hqd_load()
279 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in kgd_hqd_load()
287 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, in kgd_hqd_load()
292 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR, in kgd_hqd_load()
297 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); in kgd_hqd_load()
500 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
631 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
723 WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd); in kgd_wave_control_execute()
[all …]
A Damdgpu_amdkfd_gfx_v9.c185 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), in kgd_gfx_v9_init_interrupts()
252 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_load()
304 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), in kgd_gfx_v9_hqd_load()
389 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_dump()
674 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); in kgd_gfx_v9_wave_control_execute()
757 *vmid = (RREG32_SOC15(GC, 0, mmCP_HQD_VMID) & in get_wave_count()
842 queue_map = RREG32(SOC15_REG_OFFSET(GC, 0, in kgd_gfx_v9_get_cu_occupancy()
895 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO), in kgd_gfx_v9_program_trap_handler_settings()
897 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI), in kgd_gfx_v9_program_trap_handler_settings()
903 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO), in kgd_gfx_v9_program_trap_handler_settings()
[all …]
A Dsoc15.c298 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); in soc15_gc_cac_rreg()
309 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); in soc15_gc_cac_wreg()
320 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); in soc15_se_cac_rreg()
331 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); in soc15_se_cac_wreg()
412 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
413 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
420 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
426 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
429 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
431 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
[all …]
A Dsdma_v5_2.c551 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_2_ctx_switch_enable()
553 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_2_ctx_switch_enable()
555 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_2_ctx_switch_enable()
627 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_2_gfx_resume()
629 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_2_gfx_resume()
638 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, in sdma_v5_2_gfx_resume()
822 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in sdma_v5_2_soft_reset()
825 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in sdma_v5_2_soft_reset()
826 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in sdma_v5_2_soft_reset()
831 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in sdma_v5_2_soft_reset()
[all …]
A Dnv.c396 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
397 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
398 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
399 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
400 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
401 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
404 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
405 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
410 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
413 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
[all …]
A Dgfxhub_v1_1.c53 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE); in gfxhub_v1_1_get_xgmi_info()
55 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE), in gfxhub_v1_1_get_xgmi_info()
60 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); in gfxhub_v1_1_get_xgmi_info()
62 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), in gfxhub_v1_1_get_xgmi_info()
A Damdgpu_gmc.c658 RREG32_SOC15_IP(GC, reg) : in amdgpu_gmc_set_vm_fault_masks()
667 WREG32_SOC15_IP(GC, reg, tmp) : in amdgpu_gmc_set_vm_fault_masks()
A Damdgpu_discovery.c281 info = &bhdr->table_list[GC]; in amdgpu_discovery_init()
546 le16_to_cpu(bhdr->table_list[GC].offset)); in amdgpu_discovery_get_gfx_info()
A Dmmhub_v2_0.c324 WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); in mmhub_v2_0_init_cache_regs()
A Dmmhub_v2_3.c245 WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); in mmhub_v2_3_init_cache_regs()
/linux/Documentation/ABI/testing/
A Dsysfs-fs-f2fs126 section, it can let GC move partial segment{s} of one section
127 in one GC cycle, so that dispersing heavy overhead GC to
267 Description: Do background GC aggressively when set. When gc_urgent = 1,
268 background thread starts to do GC by given gc_urgent_sleep_time
271 and GC a little bit aggressively. It is set to 0 by default.
276 Description: Controls sleep time of GC urgent mode. Set to 500ms by default.
286 Description: This indicates how many GC can be failed for the pinned
499 Description: Show how many segments have been reclaimed by GC during a specific
500 GC mode (0: GC normal, 1: GC idle CB, 2: GC idle greedy,
501 3: GC idle AT, 4: GC urgent high, 5: GC urgent low)
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega10_powertune.c923 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_cac_driving_se_didt_config()
938 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_cac_driving_se_didt_config()
974 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_didt_config()
983 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_didt_config()
1035 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_se_edc_config()
1046 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_config()
1085 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_edc_config()
1094 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_edc_config()
1144 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_force_stall_config()
/linux/drivers/gpu/drm/amd/include/
A Ddiscovery.h34 GC, enumerator
/linux/Documentation/filesystems/
A Df2fs.rst114 let background GC thread to handle foreground GC requests,
116 GC operation when GC is triggered from a process with limited
118 nogc_merge Disable GC merge feature.
207 fragmentation/after-GC situation itself. The developers use these
208 modes to understand filesystem fragmentation/after-GC condition well,
211 position. With this, we can simulate the after-GC condition.
335 effectiveness and efficiency on background GC.
/linux/fs/jffs2/
A DREADME.Locking95 GC thread locks it, sends the signal, then unlocks it - while the GC

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