Home
last modified time | relevance | path

Searched refs:GRBM_GFX_INDEX (Results 1 – 25 of 29) sorted by relevance

12

/linux/drivers/gpu/drm/amd/amdkfd/
A Dcik_regs.h69 #define GRBM_GFX_INDEX 0x30800 macro
A Dkfd_dbgdev.c653 GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE; in dbgdev_wave_control_diq()
677 GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE; in dbgdev_wave_control_diq()
/linux/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v9_4.c99 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_select_se_sh()
102 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v9_4_select_se_sh()
106 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v9_4_select_se_sh()
109 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh()
112 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, in gfx_v9_4_select_se_sh()
115 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
A Damdgpu_amdkfd_gfx_v8.c590 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
592 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
594 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
A Dvce_v4_0.c747 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
752 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
757 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
939 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);
958 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
A Damdgpu_amdkfd_gfx_v10.c725 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
727 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
729 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
A Damdgpu_amdkfd_gfx_v9.c676 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
678 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
680 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
A Damdgpu_amdkfd_gfx_v10_3.c635 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
637 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
639 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
A Dgfx_v9_4_2.c852 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_2_select_se_sh()
855 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v9_4_2_select_se_sh()
859 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v9_4_2_select_se_sh()
862 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_2_select_se_sh()
865 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, in gfx_v9_4_2_select_se_sh()
868 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_2_select_se_sh()
A Dsoc15_common.h150 …m_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \
A Dvce_v3_0.c851 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); in vce_v3_0_get_clockgating_state()
A Dgfx_v9_0.c2495 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2497 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v9_0_select_se_sh()
2500 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2502 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh()
2505 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2507 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
A Dgfx_v8_0.c3445 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3447 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v8_0_select_se_sh()
3450 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3452 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v8_0_select_se_sh()
3455 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3457 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
A Dsid.h996 #define GRBM_GFX_INDEX 0x200B macro
A Dgfx_v6_0.c1307 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v6_0_select_se_sh()
1309 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v6_0_select_se_sh()
A Dgfx_v10_0.c4999 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v10_0_select_se_sh()
5002 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v10_0_select_se_sh()
5006 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v10_0_select_se_sh()
5009 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v10_0_select_se_sh()
5012 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, in gfx_v10_0_select_se_sh()
5015 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v10_0_select_se_sh()
/linux/drivers/gpu/drm/radeon/
A Dcypress_dpm.c125 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
152 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
186 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
207 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
A Dni.c1082 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1102 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1111 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in cayman_gpu_init()
A Dnid.h295 #define GRBM_GFX_INDEX 0x802C macro
A Dsid.h998 #define GRBM_GFX_INDEX 0x802C macro
A Dcikd.h1627 #define GRBM_GFX_INDEX 0x30800 macro
A Devergreen.c3466 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3487 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3496 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
A Devergreend.h412 #define GRBM_GFX_INDEX 0x802C macro
/linux/drivers/gpu/drm/radeon/reg_srcs/
A Dcayman2 0x0000802C GRBM_GFX_INDEX
A Devergreen2 0x0000802C GRBM_GFX_INDEX

Completed in 128 milliseconds

12