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Searched refs:I915_MAX_PLANES (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
A Dintel_atomic_plane.c431 struct skl_ddb_entry entries_y[I915_MAX_PLANES], in skl_next_plane_to_commit() argument
432 struct skl_ddb_entry entries_uv[I915_MAX_PLANES], in skl_next_plane_to_commit() argument
453 I915_MAX_PLANES, plane_id) || in skl_next_plane_to_commit()
456 I915_MAX_PLANES, plane_id)) in skl_next_plane_to_commit()
502 struct skl_ddb_entry entries_y[I915_MAX_PLANES]; in skl_update_planes_on_crtc()
503 struct skl_ddb_entry entries_uv[I915_MAX_PLANES]; in skl_update_planes_on_crtc()
A Dintel_display_types.h789 struct skl_plane_wm planes[I915_MAX_PLANES];
808 u16 plane[I915_MAX_PLANES];
861 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
862 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
1137 int min_cdclk[I915_MAX_PLANES];
1139 u32 data_rate[I915_MAX_PLANES];
1142 u64 plane_data_rate[I915_MAX_PLANES];
1143 u64 uv_plane_data_rate[I915_MAX_PLANES];
A Dintel_display.h184 I915_MAX_PLANES, enumerator
188 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
A Dintel_display.c7853 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; in verify_wm_state()
7854 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES]; in verify_wm_state()
/linux/drivers/gpu/drm/i915/gvt/
A Dreg.h92 (PLANE_SPRITE0) : (I915_MAX_PLANES))); })
/linux/drivers/gpu/drm/i915/
A Di915_drv.h755 u16 plane[I915_MAX_PLANES];
766 u8 plane[I915_MAX_PLANES];
1313 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
A Dintel_pm.c5109 u16 total[I915_MAX_PLANES] = {}; in skl_allocate_plane_ddb()
5110 u16 uv_total[I915_MAX_PLANES] = {}; in skl_allocate_plane_ddb()

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