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Searched refs:MPLL_CNTL_MODE (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/radeon/
A Drv740d.h42 #define MPLL_CNTL_MODE 0x61c macro
A Drv740_dpm.c399 WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); in rv740_enable_mclk_spread_spectrum()
401 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); in rv740_enable_mclk_spread_spectrum()
A Dcypress_dpm.c229 WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); in cypress_enable_spread_spectrum()
233 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); in cypress_enable_spread_spectrum()
234 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN); in cypress_enable_spread_spectrum()
A Drv770.c1166 tmp = RREG32(MPLL_CNTL_MODE); in rv770_set_clk_bypass_mode()
1171 WREG32(MPLL_CNTL_MODE, tmp); in rv770_set_clk_bypass_mode()
A Drv770d.h114 #define MPLL_CNTL_MODE 0x61c macro
A Dnid.h556 #define MPLL_CNTL_MODE 0x61c macro
A Dsid.h610 #define MPLL_CNTL_MODE 0x2bb0 macro
A Devergreend.h93 #define MPLL_CNTL_MODE 0x61c macro
A Dsi.c4004 tmp = RREG32(MPLL_CNTL_MODE); in si_set_clk_bypass_mode()
4006 WREG32(MPLL_CNTL_MODE, tmp); in si_set_clk_bypass_mode()
/linux/drivers/gpu/drm/amd/amdgpu/
A Dsi.c1352 tmp = RREG32(MPLL_CNTL_MODE); in si_set_clk_bypass_mode()
1354 WREG32(MPLL_CNTL_MODE, tmp); in si_set_clk_bypass_mode()
A Dsid.h611 #define MPLL_CNTL_MODE 0xAEC macro

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