Searched refs:PP_SMU_RESULT_OK (Results 1 – 4 of 4) sorted by relevance
618 return PP_SMU_RESULT_OK; in pp_nv_set_wm_ranges()635 return PP_SMU_RESULT_OK; in pp_nv_set_display_count()653 return PP_SMU_RESULT_OK; in pp_nv_set_min_deep_sleep_dcfclk()677 return PP_SMU_RESULT_OK; in pp_nv_set_hard_min_dcefclk_by_freq()701 return PP_SMU_RESULT_OK; in pp_nv_set_hard_min_uclk_by_freq()718 return PP_SMU_RESULT_OK; in pp_nv_set_pstate_handshake_support()754 return PP_SMU_RESULT_OK; in pp_nv_set_voltage_by_freq()769 return PP_SMU_RESULT_OK; in pp_nv_get_maximum_sustainable_clocks()788 return PP_SMU_RESULT_OK; in pp_nv_get_uclk_dpm_states()805 return PP_SMU_RESULT_OK; in pp_rn_get_dpm_clock_table()[all …]
62 PP_SMU_RESULT_OK = 1, enumerator
1017 if (status == PP_SMU_RESULT_OK && in rn_clk_mgr_construct()
3685 uclk_states_available = (status == PP_SMU_RESULT_OK); in init_soc_bounding_box()3695 clock_limits_available = (status == PP_SMU_RESULT_OK); in init_soc_bounding_box()
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