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Searched refs:PP_SMU_RESULT_OK (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_pp_smu.c618 return PP_SMU_RESULT_OK; in pp_nv_set_wm_ranges()
635 return PP_SMU_RESULT_OK; in pp_nv_set_display_count()
653 return PP_SMU_RESULT_OK; in pp_nv_set_min_deep_sleep_dcfclk()
677 return PP_SMU_RESULT_OK; in pp_nv_set_hard_min_dcefclk_by_freq()
701 return PP_SMU_RESULT_OK; in pp_nv_set_hard_min_uclk_by_freq()
718 return PP_SMU_RESULT_OK; in pp_nv_set_pstate_handshake_support()
754 return PP_SMU_RESULT_OK; in pp_nv_set_voltage_by_freq()
769 return PP_SMU_RESULT_OK; in pp_nv_get_maximum_sustainable_clocks()
788 return PP_SMU_RESULT_OK; in pp_nv_get_uclk_dpm_states()
805 return PP_SMU_RESULT_OK; in pp_rn_get_dpm_clock_table()
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/linux/drivers/gpu/drm/amd/display/dc/
A Ddm_pp_smu.h62 PP_SMU_RESULT_OK = 1, enumerator
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c1017 if (status == PP_SMU_RESULT_OK && in rn_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c3685 uclk_states_available = (status == PP_SMU_RESULT_OK); in init_soc_bounding_box()
3695 clock_limits_available = (status == PP_SMU_RESULT_OK); in init_soc_bounding_box()

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