Home
last modified time | relevance | path

Searched refs:RF_PATH_D (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/staging/r8188eu/hal/
A Drtl8188e_phycfg.c420 pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; in phy_InitBBRFRegisterDefinition()
426 pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ in phy_InitBBRFRegisterDefinition()
440 pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; in phy_InitBBRFRegisterDefinition()
446 pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; in phy_InitBBRFRegisterDefinition()
452 pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; in phy_InitBBRFRegisterDefinition()
458 pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; in phy_InitBBRFRegisterDefinition()
464 pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; in phy_InitBBRFRegisterDefinition()
470 pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; in phy_InitBBRFRegisterDefinition()
476 pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; in phy_InitBBRFRegisterDefinition()
482 pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; in phy_InitBBRFRegisterDefinition()
[all …]
/linux/drivers/staging/r8188eu/include/
A DHal8188EPhyCfg.h37 RF_PATH_D = 3, /* Radio Path D */ enumerator
/linux/drivers/staging/rtl8712/
A Drtl871x_mp.h141 #define RF_PATH_D 3 macro
/linux/drivers/net/wireless/realtek/rtw88/
A Dmain.h137 RF_PATH_D = 3, enumerator
/linux/drivers/net/wireless/realtek/rtw89/
A Dcore.c915 rssi[RF_PATH_D] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_D(buf)); in rtw89_core_update_phy_ppdu()
A Dcore.h494 RF_PATH_D = 3, enumerator

Completed in 42 milliseconds