/linux/drivers/gpu/drm/amd/amdgpu/ |
A D | mmhub_v9_4.c | 1527 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 }, 1528 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 }, 1529 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 }, 1530 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 }, 1531 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 }, 1533 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 }, 1536 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 }, 1539 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 }, 1542 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 }, 1545 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 }, [all …]
|
A D | gfx_v9_4.c | 52 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 }, 58 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1 }, 60 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 8, 16 }, 132 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 136 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 140 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 144 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 176 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 180 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 184 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), [all …]
|
A D | gfx_v9_4_2.c | 896 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), 900 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), 904 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), 908 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), 929 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), 933 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), 937 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), 941 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), 945 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, 948 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, [all …]
|
A D | mmhub_v1_7.c | 1186 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 }, 1187 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 }, 1188 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 }, 1189 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 }, 1190 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 }, 1191 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 }, 1192 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 }, 1193 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 }, 1195 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 }, 1198 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 }, [all …]
|
A D | sdma_v4_4.c | 60 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 64 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 68 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 72 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 76 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 80 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 84 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 124 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), 128 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), 132 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), [all …]
|
A D | mmhub_v1_0.c | 588 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 592 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 604 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 608 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 648 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 652 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 664 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 699 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0}, 700 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0}, 701 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0}, [all …]
|
A D | gfx_v9_0.c | 714 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, 715 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, 6054 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 6067 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 6072 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 6077 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6082 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6087 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6092 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6244 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), [all …]
|
A D | nv.c | 396 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 397 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 398 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 399 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 400 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 401 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 404 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 405 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 410 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 413 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, [all …]
|
A D | soc15.c | 412 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 413 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 414 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 415 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 416 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 417 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 420 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 426 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 429 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 430 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, [all …]
|
A D | sdma_v4_0.c | 296 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 300 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 304 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 308 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 316 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 320 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 324 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 328 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 332 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 336 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), [all …]
|
A D | soc15.h | 89 #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg macro
|
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
A D | vega10_baco.c | 37 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIF_FB_EN), 0, 0, 0, 0}, 45 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_EN_MASK, BACO_CNTL__B… 47 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_C… 54 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_POWER_OFF_MASK, BACO_… 58 …{CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_MODE_MASK, BACO_CNTL__BACO_MO… 63 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_POWER_OFF_MASK, BACO_… 74 …{CMD_WAITFOR, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_EXIT_MASK, 0, 0xffffff… 78 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_EN_MASK , BACO_CNTL__… 79 {CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0} 84 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0}, [all …]
|
A D | vega20_baco.c | 36 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0}, 37 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
|