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/linux/drivers/clk/sprd/
A Dgate.h32 _sc_offset, _enable_mask, _flags, \ argument
43 _ops, _flags), \
61 _enable_mask, _flags, _gate_flags) \ argument
83 _flags, _gate_flags, \ argument
91 _sc_offset, _enable_mask, _flags, \ argument
95 _flags, _gate_flags, 0, _ops)
101 _sc_offset, _enable_mask, _flags, \
111 _sc_offset, _enable_mask, _flags, \ argument
120 _enable_mask, _flags, \ argument
132 _enable_mask, _flags, \
[all …]
A Dcomposite.h23 _flags, _fn) \ argument
31 &sprd_comp_ops, _flags), \
36 _mshift, _mwidth, _dshift, _dwidth, _flags) \ argument
39 _flags, CLK_HW_INIT_PARENTS)
42 _mwidth, _dshift, _dwidth, _flags) \ argument
44 _mshift, _mwidth, _dshift, _dwidth, _flags)
48 _dwidth, _flags) \ argument
51 _flags, CLK_HW_INIT_PARENTS_DATA)
54 _mwidth, _dshift, _dwidth, _flags) \ argument
57 _flags)
A Dmux.h40 _reg, _shift, _width, _flags, _fn) \ argument
47 &sprd_mux_ops, _flags), \
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
69 _shift, _width, _flags) \ argument
71 _reg, _shift, _width, _flags)
A Ddiv.h39 _shift, _width, _flags, _fn) \ argument
46 &sprd_div_ops, _flags), \
51 _shift, _width, _flags) \ argument
53 _shift, _width, _flags, CLK_HW_INIT)
56 _shift, _width, _flags) \ argument
58 _shift, _width, _flags, CLK_HW_INIT_HW)
/linux/drivers/clk/sunxi-ng/
A Dccu_div.h47 .flags = _flags, \
58 .flags = _flags, \
99 _flags), \
109 _flags)
116 _gate, _flags) \ argument
126 _flags), \
137 _gate, _flags)
141 _flags) \ argument
146 0, _flags)
151 _flags) \ argument
[all …]
A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
27 _flags), \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
39 _flags), \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
51 _flags), \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
67 _flags), \
71 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
80 _flags), \
A Dccu_mp.h38 _gate, _postdiv, _flags) \ argument
51 _flags), \
59 _gate, _flags) \ argument
70 _flags), \
78 _flags) \ argument
83 0, _flags)
104 _flags) \ argument
117 _flags), \
A Dccu_nm.h43 _gate, _lock, _flags) \ argument
57 _flags), \
66 _gate, _lock, _flags) \ argument
81 _flags), \
91 _gate, _lock, _flags) \ argument
107 _flags), \
119 _gate, _lock, _flags) \ argument
136 _flags), \
143 _gate, _lock, _flags) \ argument
154 _flags), \
A Dccu_mux.h51 _flags) \ argument
60 _flags), \
65 _shift, _width, _gate, _flags) \ argument
68 _flags)
71 _flags) \ argument
73 _reg, _shift, _width, 0, _flags)
A Dccu_nkm.h39 _gate, _lock, _flags) \ argument
52 _flags), \
60 _gate, _lock, _flags) \ argument
72 _flags), \
/linux/drivers/clk/actions/
A Dowl-composite.h38 _mux, _gate, _div, _flags) \ argument
48 _flags), \
53 _gate, _div, _flags) \ argument
62 _flags), \
67 _mux, _gate, _factor, _flags) \ argument
77 _flags), \
82 _gate, _mul, _div, _flags) \ argument
93 _flags), \
98 _mux, _gate, _flags) \ argument
107 _flags), \
A Dowl-pll.h56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
66 _flags), \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
80 _flags), \
86 _flags) \ argument
95 _flags), \
A Dowl-gate.h35 _bit_idx, _gate_flags, _flags) \ argument
43 _flags), \
48 _bit_idx, _gate_flags, _flags) \ argument
55 _flags), \
/linux/drivers/gpu/drm/amd/pm/inc/
A Damdgpu_pm.h63 #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \ argument
65 .flags = _flags, \
68 #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \ argument
71 _flags, ##__VA_ARGS__)
73 #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \ argument
75 _flags, ##__VA_ARGS__)
77 #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \ argument
80 _flags, ##__VA_ARGS__)
/linux/drivers/staging/media/atomisp/include/media/
A Dlm3554.h29 _default_value, _flags) \ argument
38 .flags = (_flags),\
41 _default_value, _flags) \ argument
50 .flags = (_flags),\
55 _default_value, _flags, \ argument
60 _default_value, _flags), \
66 _default_value, _flags, \ argument
70 _default_value, _flags), \
/linux/include/linux/
A Dtimer.h76 #define __TIMER_INITIALIZER(_function, _flags) { \ argument
79 .flags = (_flags), \
112 #define __init_timer(_timer, _fn, _flags) \ argument
115 init_timer_key((_timer), (_fn), (_flags), #_timer, &__key);\
118 #define __init_timer_on_stack(_timer, _fn, _flags) \ argument
121 init_timer_on_stack_key((_timer), (_fn), (_flags), \
125 #define __init_timer(_timer, _fn, _flags) \ argument
126 init_timer_key((_timer), (_fn), (_flags), NULL, NULL)
127 #define __init_timer_on_stack(_timer, _fn, _flags) \ argument
128 init_timer_on_stack_key((_timer), (_fn), (_flags), NULL, NULL)
A Dirqflags.h110 # define lockdep_irq_work_enter(_flags) \ argument
112 if (!((_flags) & IRQ_WORK_HARD_IRQ)) \
115 # define lockdep_irq_work_exit(_flags) \ argument
117 if (!((_flags) & IRQ_WORK_HARD_IRQ)) \
253 unsigned long _flags; \
254 raw_local_save_flags(_flags); \
255 raw_irqs_disabled_flags(_flags); \
A Dsh_clk.h117 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ argument
123 .flags = _flags, \
151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
158 .flags = _flags, \
175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
180 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
194 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
A Dclk-provider.h1260 .flags = _flags, \
1269 .flags = _flags, \
1283 .flags = _flags, \
1292 .flags = _flags, \
1303 .flags = _flags, \
1312 .flags = _flags, \
1321 .flags = _flags, \
1345 _flags), \
1356 _flags), \
1371 _flags), \
[all …]
/linux/include/linux/gpio/
A Dmachine.h69 #define GPIO_LOOKUP(_key, _chip_hwnum, _con_id, _flags) \ argument
70 GPIO_LOOKUP_IDX(_key, _chip_hwnum, _con_id, 0, _flags)
77 #define GPIO_LOOKUP_IDX(_key, _chip_hwnum, _con_id, _idx, _flags) \ argument
83 .flags = _flags, \
/linux/drivers/net/wireless/ath/ath5k/
A Dath5k.h112 #define AR5K_REG_SM(_val, _flags) \ argument
113 (((_val) << _flags##_S) & (_flags))
116 #define AR5K_REG_MS(_val, _flags) \ argument
117 (((_val) & (_flags)) >> _flags##_S)
124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ argument
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
126 (((_val) << _flags##_S) & (_flags)), _reg)
128 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ argument
130 (_mask)) | (_flags), _reg)
132 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ argument
[all …]
/linux/drivers/clk/mediatek/
A Dclk-mtk.h83 _width, _gate, _flags, _muxflags) { \ argument
94 .flags = _flags, \
103 _gate, _flags) \ argument
105 _shift, _width, _gate, _flags, 0)
119 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
129 .flags = _flags, \
A Dclk-mux.h42 _gate, _upd_ofs, _upd, _flags, _ops) { \ argument
55 .flags = _flags, \
64 _gate, _upd_ofs, _upd, _flags) \ argument
67 _gate, _upd_ofs, _upd, _flags, \
A Dclk-mt6797.c434 #define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \ argument
441 .flags = _flags, \
447 #define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \ argument
454 .flags = _flags, \
609 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
617 .flags = _flags, \
629 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
632 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
/linux/drivers/mtd/spi-nor/
A Dcore.h393 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ argument
405 .flags = (_flags),
407 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ argument
420 .flags = (_flags),
422 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ argument
427 .flags = (_flags),

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