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/linux/arch/arm/mach-pxa/include/mach/
A Dhardware.h107 _id == 0x2120; \
113 _id <= 0x2105; \
119 _id == 0x2d06; \
125 _id == 0x2100; \
138 _id == 0x411; \
148 _id == 0x688; \
158 _id == 0x689; \
168 _id == 0x603 || _id == 0x682; \
178 _id == 0x683; \
188 _id == 0x693; \
[all …]
/linux/drivers/clk/renesas/
A Drzg2l-cpg.h85 #define DEF_TYPE(_name, _id, _type...) \ argument
86 { .name = _name, .id = _id, .type = _type }
87 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
88 DEF_TYPE(_name, _id, _type, .parent = _parent)
89 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
91 #define DEF_INPUT(_name, _id) \ argument
92 DEF_TYPE(_name, _id, CLK_TYPE_IN)
129 .id = MOD_CLK_BASE + (_id), \
136 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ argument
153 #define DEF_RST(_id, _off, _bit) \ argument
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A Drcar-gen3-cpg.h35 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
36 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
39 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
45 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
48 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
49 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
52 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
55 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
56 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
58 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ argument
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A Drenesas-cpg-mssr.h44 #define DEF_TYPE(_name, _id, _type...) \ argument
45 { .name = _name, .id = _id, .type = _type }
46 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
47 DEF_TYPE(_name, _id, _type, .parent = _parent)
49 #define DEF_INPUT(_name, _id) \ argument
50 DEF_TYPE(_name, _id, CLK_TYPE_IN)
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
57 #define DEF_RATE(_name, _id, _rate) \ argument
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/linux/arch/powerpc/include/asm/
A Dperf_event_server.h170 #define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix argument
171 #define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr argument
173 #define EVENT_ATTR(_name, _id, _suffix) \ argument
174 PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), _id, \
177 #define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g) argument
178 #define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g) argument
180 #define CACHE_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _c) argument
181 #define CACHE_EVENT_PTR(_id) EVENT_PTR(_id, _c) argument
183 #define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _p) argument
184 #define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p) argument
/linux/drivers/clk/samsung/
A Dclk.h42 #define ALIAS(_id, dname, a) \ argument
44 .id = _id, \
69 .id = _id, \
96 .id = _id, \
130 .id = _id, \
142 __MUX(_id, cname, pnames, o, s, w, 0, 0)
171 .id = _id, \
213 .id = _id, \
223 __GATE(_id, cname, pname, o, b, f, gf)
260 .id = _id, \
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/linux/include/linux/
A Dmod_devicetable.h427 #define BCMA_CORE(_manuf, _id, _rev, _class) \ argument
428 { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
602 #define MDIO_ID_ARGS(_id) \ argument
603 ((_id)>>31) & 1, ((_id)>>30) & 1, ((_id)>>29) & 1, ((_id)>>28) & 1, \
604 ((_id)>>27) & 1, ((_id)>>26) & 1, ((_id)>>25) & 1, ((_id)>>24) & 1, \
605 ((_id)>>23) & 1, ((_id)>>22) & 1, ((_id)>>21) & 1, ((_id)>>20) & 1, \
606 ((_id)>>19) & 1, ((_id)>>18) & 1, ((_id)>>17) & 1, ((_id)>>16) & 1, \
607 ((_id)>>15) & 1, ((_id)>>14) & 1, ((_id)>>13) & 1, ((_id)>>12) & 1, \
608 ((_id)>>11) & 1, ((_id)>>10) & 1, ((_id)>>9) & 1, ((_id)>>8) & 1, \
609 ((_id)>>7) & 1, ((_id)>>6) & 1, ((_id)>>5) & 1, ((_id)>>4) & 1, \
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/linux/drivers/clk/rockchip/
A Dclk.h465 .id = _id, \
486 .id = _id, \
508 .id = _id, \
526 .id = _id, \
545 .id = _id, \
563 .id = _id, \
582 .id = _id, \
601 .id = _id, \
618 .id = _id, \
636 .id = _id, \
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/linux/drivers/clk/mediatek/
A Dclk-mt8195-infra_ao.c44 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
47 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
48 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
51 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
54 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
55 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
57 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
64 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
65 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
71 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
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A Dclk-mtk.h30 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
31 .id = _id, \
48 #define FACTOR(_id, _name, _parent, _mult, _div) { \ argument
49 .id = _id, \
84 .id = _id, \
104 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
115 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
116 MUX_FLAGS(_id, _name, _parents, _reg, \
120 .id = _id, \
134 .id = _id, \
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A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
A Dclk-mt8192.c923 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
930 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
931 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
933 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
940 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
941 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
943 #define GATE_INFRA4(_id, _name, _parent, _shift) \ argument
950 #define GATE_INFRA5(_id, _name, _parent, _shift) \ argument
1095 #define GATE_PERI(_id, _name, _parent, _shift) \ argument
1108 #define GATE_TOP(_id, _name, _parent, _shift) \ argument
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A Dclk-mt8167.c658 .id = _id, \
688 .id = _id, \
739 .id = _id, \
748 .id = _id, \
757 .id = _id, \
766 .id = _id, \
775 .id = _id, \
784 .id = _id, \
793 .id = _id, \
802 .id = _id, \
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A Dclk-mux.h40 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
43 .id = _id, \
62 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
65 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
70 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ argument
73 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
78 #define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ argument
81 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
/linux/drivers/clk/pistachio/
A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
21 .id = _id, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
41 .id = _id, \
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
61 .id = _id, \
71 .id = _id, \
86 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
88 .id = _id, \
121 .id = _id, \
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/linux/drivers/regulator/
A Dmax77826-regulator.c119 #define MAX77826_LDO(_id, _type) \ argument
120 [MAX77826_LDO ## _id] = { \
121 .id = MAX77826_LDO ## _id, \
122 .name = "LDO"#_id, \
123 .of_match = of_match_ptr("LDO"#_id), \
136 #define MAX77826_BUCK(_idx, _id, _ops) \ argument
137 [MAX77826_ ## _id] = { \
138 .id = MAX77826_ ## _id, \
139 .name = #_id, \
140 .of_match = of_match_ptr(#_id), \
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A Drtq2134-regulator.c26 #define RTQ2134_REG_FLT_RECORDBUCK(_id) (0x14 + (_id)) argument
27 #define RTQ2134_REG_FLT_BUCKCTRL(_id) (0x37 + (_id)) argument
270 #define RTQ2134_BUCK_DESC(_id) { \ argument
272 .name = "rtq2134_buck" #_id, \
273 .of_match = of_match_ptr("buck" #_id), \
275 .id = RTQ2134_IDX_BUCK##_id, \
282 .vsel_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG1, \
284 .enable_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG0, \
288 .ramp_reg = RTQ2134_REG_BUCK##_id##_RSPCFG, \
295 .mode_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG0, \
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A Dmpq7920.c27 #define MPQ7920BUCK(_name, _id, _ilim) \ argument
28 [MPQ7920_BUCK ## _id] = { \
29 .id = MPQ7920_BUCK ## _id, \
40 .csel_reg = MPQ7920_BUCK ##_id## _REG_C, \
44 MPQ7920_BUCK ## _id), \
45 .vsel_reg = MPQ7920_BUCK ##_id## _REG_A, \
50 .soft_start_reg = MPQ7920_BUCK ##_id## _REG_C, \
56 [MPQ7920_LDO ## _id] = { \
57 .id = MPQ7920_LDO ## _id, \
65 .vsel_reg = MPQ7920_LDO ##_id## _REG_A, \
[all …]
A Dhi6421-regulator.c131 [HI6421_##_id] = { \
133 .name = #_id, \
138 .id = HI6421_##_id, \
170 [HI6421_##_id] = { \
172 .name = #_id, \
210 [HI6421_##_id] = { \
212 .name = #_id, \
247 [HI6421_##_id] = { \
249 .name = #_id, \
284 [HI6421_##_id] = { \
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A Dmp5416.c52 #define MP5416BUCK(_name, _id, _ilim, _dreg, _dval, _vsel) \ argument
53 [MP5416_BUCK ## _id] = { \
54 .id = MP5416_BUCK ## _id, \
65 .csel_mask = MP5416_MASK_BUCK ## _id ##_ILIM, \
66 .vsel_reg = MP5416_REG_BUCK ## _id, \
68 .enable_reg = MP5416_REG_BUCK ## _id, \
80 #define MP5416LDO(_name, _id, _dval) \ argument
81 [MP5416_LDO ## _id] = { \
82 .id = MP5416_LDO ## _id, \
90 .vsel_reg = MP5416_REG_LDO ##_id, \
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/linux/sound/soc/mediatek/mt8195/
A Dmt8195-audsys-clk.c29 .id = _id, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
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/linux/include/rdma/
A Duverbs_std_types.h19 #define _uobj_check_id(_id) ((_id) * typecheck(u32, _id)) argument
24 #define uobj_get_read(_type, _id, _attrs) \ argument
26 _uobj_check_id(_id), UVERBS_LOOKUP_READ, \
40 #define uobj_get_obj_read(_object, _type, _id, _attrs) \ argument
42 uobj_get_read(_type, _id, _attrs)))
44 #define uobj_get_write(_type, _id, _attrs) \ argument
46 _uobj_check_id(_id), UVERBS_LOOKUP_WRITE, \
51 #define uobj_perform_destroy(_type, _id, _attrs) \ argument
53 _uobj_check_id(_id), _attrs)
58 #define uobj_get_destroy(_type, _id, _attrs) \ argument
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/linux/include/linux/mfd/
A Dcore.h17 #define MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, _use_of_reg, _match) \ argument
28 .id = (_id), \
31 #define MFD_CELL_OF_REG(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg) \ argument
32 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, true, NULL)
34 #define MFD_CELL_OF(_name, _res, _pdata, _pdsize, _id, _compat) \ argument
35 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, 0, false, NULL)
37 #define MFD_CELL_ACPI(_name, _res, _pdata, _pdsize, _id, _match) \ argument
38 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, _match)
40 #define MFD_CELL_BASIC(_name, _res, _pdata, _pdsize, _id) \ argument
41 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, NULL)
/linux/drivers/staging/media/atomisp/include/media/
A Dlm3554.h27 #define v4l2_queryctrl_entry_integer(_id, _name,\ argument
31 .id = (_id), \
40 #define v4l2_queryctrl_entry_boolean(_id, _name,\ argument
43 .id = (_id), \
53 #define s_ctrl_id_entry_integer(_id, _name, \ argument
58 .qc = v4l2_queryctrl_entry_integer(_id, _name,\
65 #define s_ctrl_id_entry_boolean(_id, _name, \ argument
69 .qc = v4l2_queryctrl_entry_boolean(_id, _name,\
/linux/drivers/clk/x86/
A Dclk-cgu.h122 #define LGM_PLL(_id, _name, _pdata, _flags, \ argument
125 .id = _id, \
155 .id = _id, \
206 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \ argument
209 .id = _id, \
225 .id = _id, \
244 #define LGM_GATE(_id, _name, _pname, _f, _reg, \ argument
247 .id = _id, \
262 #define LGM_FIXED(_id, _name, _pname, _f, _reg, \ argument
265 .id = _id, \
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1234567891011