/linux/drivers/clk/pistachio/ |
A D | clk.h | 19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument 25 .parent = _pname, \ 59 #define DIV(_id, _name, _pname, _reg, _width) \ argument 66 .parent = _pname, \ 76 .parent = _pname, \ 86 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument 91 .parent = _pname, \ 119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument 127 .parent = _pname, \ 130 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument [all …]
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/linux/drivers/clk/x86/ |
A D | clk-cgu.h | 158 .fw_name = _pname, \ 159 .name = _pname, \ 229 .fw_name = _pname, \ 230 .name = _pname, \ 251 .fw_name = _pname, \ 252 .name = _pname, \ 254 .num_parents = !_pname ? 0 : 1, \ 269 .fw_name = _pname, \ 270 .name = _pname, \ 289 .fw_name = _pname, \ [all …]
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/linux/drivers/clk/meson/ |
A D | clk-regmap.h | 117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument 126 .parent_hws = (const struct clk_hw *[]) { _pname }, \ 132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument 133 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) 135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument 136 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
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A D | axg-audio.c | 23 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ argument 31 .parent_names = (const char *[]){ #_pname }, \ 53 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ argument 63 .parent_names = (const char *[]){ #_pname }, \ 83 _hi_shift, _hi_width, _pname, _iflags) { \ argument 99 .parent_names = (const char *[]){ #_pname }, \ 106 _pname, _iflags) { \ argument 127 .parent_names = (const char *[]){ #_pname }, \ 133 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ argument 144 .parent_names = (const char *[]){ #_pname }, \ [all …]
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/linux/drivers/regulator/ |
A D | tps6586x-regulator.c | 157 #define TPS6586X_LDO(_id, _pname, vdata, vreg, shift, nbits, \ argument 160 TPS6586X_REGULATOR(_id, rw, _pname, vdata, vreg, shift, nbits, \ 164 #define TPS6586X_LDO_LINEAR(_id, _pname, n_volt, min_uv, uv_step, vreg, \ argument 167 TPS6586X_REGULATOR_LINEAR(_id, rw_linear, _pname, n_volt, \ 172 #define TPS6586X_FIXED_LDO(_id, _pname, vdata, vreg, shift, nbits, \ argument 175 TPS6586X_REGULATOR(_id, ro, _pname, vdata, vreg, shift, nbits, \ 179 #define TPS6586X_DVM(_id, _pname, n_volt, min_uv, uv_step, vreg, shift, \ argument 182 TPS6586X_REGULATOR_LINEAR(_id, rw_linear, _pname, n_volt, \
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/linux/drivers/clk/baikal-t1/ |
A D | clk-ccu-div.c | 57 #define CCU_DIV_VAR_INFO(_id, _name, _pname, _base, _width, _flags, _features) \ argument 61 .parent_name = _pname, \ 69 #define CCU_DIV_GATE_INFO(_id, _name, _pname, _base, _divider) \ argument 73 .parent_name = _pname, \ 79 #define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider) \ argument 83 .parent_name = _pname, \
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A D | clk-ccu-pll.c | 34 #define CCU_PLL_INFO(_id, _name, _pname, _base, _flags) \ argument 38 .parent_name = _pname, \
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/linux/drivers/clk/samsung/ |
A D | clk.h | 258 #define __PLL(_typ, _id, _name, _pname, _flags, _lock, _con, _rtable) \ argument 263 .parent_name = _pname, \ 270 #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \ argument 271 __PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock, \
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/linux/drivers/scsi/ufs/ |
A D | ufs-sysfs.c | 909 #define UFS_STRING_DESCRIPTOR(_name, _pname) \ argument 937 index = desc_buf[DEVICE_DESC_PARAM##_pname]; \ 1148 #define UFS_LUN_DESC_PARAM(_pname, _puname, _duname, _size) \ argument 1149 static ssize_t _pname##_show(struct device *dev, \ 1161 static DEVICE_ATTR_RO(_pname)
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/linux/drivers/clk/ralink/ |
A D | clk-mt7621.c | 59 #define GATE(_id, _name, _pname, _shift) \ argument 63 .parent_name = _pname, \
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