| /linux/drivers/clk/ux500/ |
| A D | u8500_of_clk.c | 55 u32 bases[CLKRST_MAX]; in u8500_clk_init() local
68 for (i = 0; i < ARRAY_SIZE(bases); i++) { in u8500_clk_init()
75 bases[i] = r.start; in u8500_clk_init()
443 bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE); in u8500_clk_init()
447 bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE); in u8500_clk_init()
451 bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE); in u8500_clk_init()
455 bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE); in u8500_clk_init()
459 bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE); in u8500_clk_init()
463 bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE); in u8500_clk_init()
505 bases[CLKRST2_INDEX], BIT(6), in u8500_clk_init()
[all …]
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| /linux/drivers/iommu/ |
| A D | rockchip-iommu.c | 108 void __iomem **bases; member
431 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_stall()
452 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_stall()
473 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_paging()
494 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_paging()
564 void __iomem *base = iommu->bases[index]; in log_iova()
970 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, in rk_iommu_enable()
1231 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases), in rk_iommu_probe()
1233 if (!iommu->bases) in rk_iommu_probe()
1241 if (IS_ERR(iommu->bases[i])) in rk_iommu_probe()
[all …]
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| /linux/include/linux/ |
| A D | posix-timers.h | 131 struct posix_cputimer_base bases[CPUCLOCK_MAX]; member
149 pct->bases[0].nextevt = U64_MAX; in posix_cputimers_init()
150 pct->bases[1].nextevt = U64_MAX; in posix_cputimers_init()
151 pct->bases[2].nextevt = U64_MAX; in posix_cputimers_init()
159 pct->bases[CPUCLOCK_SCHED].nextevt = runtime; in posix_cputimers_rt_watchdog()
175 .bases = INIT_CPU_TIMERBASES(s.posix_cputimers.bases), \
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| /linux/drivers/gpu/host1x/ |
| A D | syncpt.c | 25 struct host1x_syncpt_base *bases = host->bases; in host1x_syncpt_base_request() local
29 if (!bases[i].requested) in host1x_syncpt_base_request()
35 bases[i].requested = true; in host1x_syncpt_base_request()
36 return &bases[i]; in host1x_syncpt_base_request()
336 struct host1x_syncpt_base *bases; in host1x_syncpt_init() local
345 bases = devm_kcalloc(host->dev, host->info->nb_bases, sizeof(*bases), in host1x_syncpt_init()
347 if (!bases) in host1x_syncpt_init()
363 bases[i].id = i; in host1x_syncpt_init()
367 host->bases = bases; in host1x_syncpt_init()
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| A D | dev.h | 118 struct host1x_syncpt_base *bases; member
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| /linux/drivers/gpu/drm/nouveau/dispnv50/ |
| A D | base.c | 33 } bases[] = { in nv50_base_new() local
46 cid = nvif_mclass(&disp->disp->object, bases); in nv50_base_new()
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw); in nv50_base_new()
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| /linux/drivers/iommu/arm/arm-smmu/ |
| A D | arm-smmu-nvidia.c | 36 void __iomem *bases[MAX_SMMU_INSTANCES]; member
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
294 nvidia_smmu->bases[0] = smmu->base; in nvidia_smmu_impl_init()
302 nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res); in nvidia_smmu_impl_init()
303 if (IS_ERR(nvidia_smmu->bases[i])) in nvidia_smmu_impl_init()
304 return ERR_CAST(nvidia_smmu->bases[i]); in nvidia_smmu_impl_init()
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| /linux/kernel/time/ |
| A D | posix-cpu-timers.c | 147 return !(~pct->bases[CPUCLOCK_PROF].nextevt | in expiry_cache_is_inactive()
148 ~pct->bases[CPUCLOCK_VIRT].nextevt | in expiry_cache_is_inactive()
149 ~pct->bases[CPUCLOCK_SCHED].nextevt); in expiry_cache_is_inactive()
416 return tsk->posix_cputimers.bases + clkidx; in timer_base()
418 return tsk->signal->posix_cputimers.bases + clkidx; in timer_base()
853 struct posix_cputimer_base *base = pct->bases; in collect_posix_cputimers()
999 &pct->bases[CPUCLOCK_PROF].nextevt, in check_process_timers()
1002 &pct->bases[CPUCLOCK_VIRT].nextevt, in check_process_timers()
1025 if (softns < pct->bases[CPUCLOCK_PROF].nextevt) in check_process_timers()
1026 pct->bases[CPUCLOCK_PROF].nextevt = softns; in check_process_timers()
[all …]
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| A D | tick-internal.h | 176 void clock_was_set(unsigned int bases);
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| A D | hrtimer.c | 945 void clock_was_set(unsigned int bases) in clock_was_set() argument
967 if (update_needs_ipi(cpu_base, bases)) in clock_was_set()
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| /linux/arch/x86/boot/ |
| A D | early_serial_console.c | 77 static const int bases[] = { 0x3f8, 0x2f8 }; in parse_earlyprintk() local
86 port = bases[idx]; in parse_earlyprintk()
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| /linux/drivers/gpu/drm/exynos/ |
| A D | exynos_drm_scaler.c | 154 static unsigned int bases[] = { in scaler_set_src_base() local
162 scaler_write(src_buf->dma_addr[i], bases[i]); in scaler_set_src_base()
217 static unsigned int bases[] = { in scaler_set_dst_base() local
225 scaler_write(dst_buf->dma_addr[i], bases[i]); in scaler_set_dst_base()
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| /linux/arch/x86/kernel/ |
| A D | early_printk.c | 162 static const int __initconst bases[] = { 0x3f8, 0x2f8 }; in early_serial_init() local
169 early_serial_base = bases[port]; in early_serial_init()
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| /linux/Documentation/devicetree/bindings/cpufreq/ |
| A D | cpufreq-mediatek-hw.yaml | 25 Addresses and sizes for the memory of the HW bases in
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| A D | cpufreq-qcom-hw.txt | 26 Definition: Addresses and sizes for the memory of the HW bases in
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| A D | mediatek,sysirq.txt | 31 mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
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| /linux/drivers/net/wireless/broadcom/b43/ |
| A D | pio.c | 82 static const u16 bases[] = { in index_to_pioqueue_base() local
105 B43_WARN_ON(index >= ARRAY_SIZE(bases)); in index_to_pioqueue_base()
106 return bases[index]; in index_to_pioqueue_base()
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| /linux/drivers/platform/mellanox/ |
| A D | Kconfig | 33 are defined per system type bases and include the registers related
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| /linux/drivers/gpu/drm/i915/gt/ |
| A D | intel_engine_cs.c | 241 const struct engine_mmio_base *bases) in __engine_mmio_base() argument
246 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver) in __engine_mmio_base()
250 GEM_BUG_ON(!bases[i].base); in __engine_mmio_base()
252 return bases[i].base; in __engine_mmio_base()
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| /linux/drivers/gpu/drm/msm/ |
| A D | NOTES | 58 register interface is same, just different bases.)
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| /linux/sound/pci/hda/ |
| A D | hda_proc.c | 249 static const char * const bases[7] = { in get_jack_location() local
266 return bases[cfg & 0x0f]; in get_jack_location()
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| /linux/Documentation/timers/ |
| A D | highres.rst | 169 decision is made per timer base and synchronized across per-cpu timer bases in
171 clock event devices for the per-CPU timer bases, but currently only one
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| /linux/Documentation/driver-api/thermal/ |
| A D | cpu-idle-cooling.rst | 89 The implementation of the cooling device bases the number of states on
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| /linux/Documentation/x86/ |
| A D | intel_txt.rst | 68 static root of trust must be used. This bases trust in BIOS
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| /linux/drivers/media/usb/gspca/ |
| A D | Kconfig | 442 Say Y here if you want support for Xirlink C-It bases cameras.
|