Searched refs:cfgcr0 (Results 1 – 4 of 4) sorted by relevance
/linux/drivers/gpu/drm/i915/display/ |
A D | intel_dpll_mgr.h | 208 u32 cfgcr0; member
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A D | intel_dpll_mgr.c | 2674 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * in icl_ddi_combo_pll_get_freq() 2677 dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in icl_ddi_combo_pll_get_freq() 2702 pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | in icl_calc_dpll_state() 3464 hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state() 3467 hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state() 3470 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state() 3475 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state() 3481 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state() 3486 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state() 3544 intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write() [all …]
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A D | intel_display_debugfs.c | 1113 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); in i915_shared_dplls_info()
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A D | intel_display.c | 7742 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()
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