Searched refs:clear_state_gpu_addr (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_rlc.c | 135 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_init_csb()
267 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_fini()
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| A D | amdgpu_rlc.h | 144 uint64_t clear_state_gpu_addr; member
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| A D | gfx_v6_0.c | 2404 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v6_0_rlc_init()
2414 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; in gfx_v6_0_rlc_init()
2826 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2933 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
2941 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
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| A D | gfx_v7_0.c | 3904 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3905 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
4565 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
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| A D | gfx_v10_0.c | 4442 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
5309 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
5311 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
5315 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
5317 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
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| A D | gfx_v8_0.c | 2103 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
3912 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3914 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
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| A D | gfx_v9_0.c | 2471 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_sw_fini()
2734 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb()
2736 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
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| /linux/drivers/gpu/drm/radeon/ |
| A D | evergreen.c | 4268 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init()
4287 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init()
4294 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init()
4414 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
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| A D | si.c | 5284 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5781 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5787 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
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| A D | radeon.h | 993 uint64_t clear_state_gpu_addr; member
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| A D | cik.c | 6618 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6619 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
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