/linux/drivers/clk/imx/ |
A D | clk-imx6sx.c | 177 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init() 178 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init() 179 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init() 180 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init() 181 clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk); in imx6sx_clocks_init() 182 clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); in imx6sx_clocks_init() 183 clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); in imx6sx_clocks_init() 514 clk_set_parent(hws[IMX6SX_CLK_ENET_SEL]->clk, hws[IMX6SX_CLK_ENET_PODF]->clk); in imx6sx_clocks_init() 542 clk_set_parent(hws[IMX6SX_CLK_CAN_SEL]->clk, hws[IMX6SX_CLK_PLL3_60M]->clk); in imx6sx_clocks_init() 548 clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk); in imx6sx_clocks_init() [all …]
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A D | clk-imx6q.c | 270 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, in mmdc_ch1_disable() 494 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); in imx6q_clocks_init() 495 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); in imx6q_clocks_init() 496 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); in imx6q_clocks_init() 497 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); in imx6q_clocks_init() 498 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); in imx6q_clocks_init() 964 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, in imx6q_clocks_init() 966 clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, in imx6q_clocks_init() 969 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, in imx6q_clocks_init() 971 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk, in imx6q_clocks_init() [all …]
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A D | clk-imx6ul.c | 166 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init() 167 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init() 168 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init() 169 clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk); in imx6ul_clocks_init() 170 clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk); in imx6ul_clocks_init() 171 clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk); in imx6ul_clocks_init() 172 clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk); in imx6ul_clocks_init() 489 clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_CLK2]->clk); in imx6ul_clocks_init() 491 clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_PRE]->clk); in imx6ul_clocks_init() 497 clk_set_parent(hws[IMX6UL_CLK_PERCLK_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); in imx6ul_clocks_init() [all …]
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A D | clk-vf610.c | 236 clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]); in vf610_clocks_init() 237 clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]); in vf610_clocks_init() 238 clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]); in vf610_clocks_init() 239 clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]); in vf610_clocks_init() 240 clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]); in vf610_clocks_init() 241 clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]); in vf610_clocks_init() 242 clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]); in vf610_clocks_init() 457 clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); in vf610_clocks_init() 458 clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); in vf610_clocks_init() 459 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); in vf610_clocks_init() [all …]
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A D | clk-imx6sl.c | 234 clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk); in imx6sl_clocks_init() 235 clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk); in imx6sl_clocks_init() 236 clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk); in imx6sl_clocks_init() 237 clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk); in imx6sl_clocks_init() 238 clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk); in imx6sl_clocks_init() 239 clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk); in imx6sl_clocks_init() 240 clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk); in imx6sl_clocks_init() 434 clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk); in imx6sl_clocks_init() 437 clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk, in imx6sl_clocks_init() 440 clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk, in imx6sl_clocks_init()
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A D | clk-cpu.c | 48 ret = clk_set_parent(cpu->mux, cpu->step); in clk_cpu_set_rate() 55 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate() 59 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
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A D | clk-imx5.c | 277 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); in mx5_clocks_common_init() 347 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx50_clocks_init() 348 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx50_clocks_init() 438 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init() 441 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init() 442 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init() 592 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx53_clocks_init() 593 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx53_clocks_init() 600 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init() 603 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init()
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A D | clk-imx7d.c | 871 clk_set_parent(hws[IMX7D_PLL_ARM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ARM_MAIN]->clk); in imx7d_clocks_init() 872 clk_set_parent(hws[IMX7D_PLL_DRAM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_DRAM_MAIN]->clk); in imx7d_clocks_init() 873 clk_set_parent(hws[IMX7D_PLL_SYS_MAIN_BYPASS]->clk, hws[IMX7D_PLL_SYS_MAIN]->clk); in imx7d_clocks_init() 874 clk_set_parent(hws[IMX7D_PLL_ENET_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ENET_MAIN]->clk); in imx7d_clocks_init() 875 clk_set_parent(hws[IMX7D_PLL_AUDIO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_AUDIO_MAIN]->clk); in imx7d_clocks_init() 876 clk_set_parent(hws[IMX7D_PLL_VIDEO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_VIDEO_MAIN]->clk); in imx7d_clocks_init() 878 clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk); in imx7d_clocks_init() 881 clk_set_parent(hws[IMX7D_GPT1_ROOT_SRC]->clk, hws[IMX7D_OSC_24M_CLK]->clk); in imx7d_clocks_init()
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A D | clk-imx6sll.c | 349 clk_set_parent(hws[IMX6SLL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6SLL_CLK_PLL3_USB_OTG]->clk); in imx6sll_clocks_init() 350 clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_CLK2]->clk); in imx6sll_clocks_init() 351 clk_set_parent(hws[IMX6SLL_CLK_PERIPH_PRE]->clk, hws[IMX6SLL_CLK_PLL2_BUS]->clk); in imx6sll_clocks_init() 352 clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_PRE]->clk); in imx6sll_clocks_init()
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/linux/sound/soc/mediatek/mt8183/ |
A D | mt8183-afe-clk.c | 134 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8183_afe_enable_clock() 150 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8183_afe_enable_clock() 243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 292 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting() 297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting() 352 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting() 366 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting() 371 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting() [all …]
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/linux/sound/soc/mediatek/mt8192/ |
A D | mt8192-afe-clk.c | 69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8192_set_audio_int_bus_parent() 92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 108 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting() 117 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting() 127 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting() 154 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting() 170 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting() 189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting() 231 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8192_afe_enable_clock() 255 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H], in mt8192_afe_enable_clock() [all …]
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/linux/drivers/cpufreq/ |
A D | imx6q-cpufreq.c | 128 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target() 130 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target() 133 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target() 135 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); in imx6q_set_target() 136 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target() 139 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target() 142 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); in imx6q_set_target() 143 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target() 146 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
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A D | tegra124-cpufreq.c | 38 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll() 44 clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpu_switch_to_dfll() 49 clk_set_parent(priv->cpu_clk, orig_parent); in tegra124_cpu_switch_to_dfll() 142 err = clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpufreq_suspend() 168 err = clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpufreq_resume()
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A D | imx-cpufreq-dt.c | 66 clk_set_parent(imx7ulp_clks[SCS_SEL].clk, imx7ulp_clks[FIRC].clk); in imx7ulp_target_intermediate() 67 clk_set_parent(imx7ulp_clks[HSRUN_SCS_SEL].clk, imx7ulp_clks[FIRC].clk); in imx7ulp_target_intermediate() 70 clk_set_parent(imx7ulp_clks[ARM].clk, in imx7ulp_target_intermediate() 73 clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk); in imx7ulp_target_intermediate()
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A D | mediatek-cpufreq.c | 250 ret = clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target() 264 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target() 270 ret = clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target() 288 clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target() 290 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
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A D | kirkwood-cpufreq.c | 65 clk_set_parent(priv.powersave_clk, priv.cpu_clk); in kirkwood_cpufreq_target() 68 clk_set_parent(priv.powersave_clk, priv.ddr_clk); in kirkwood_cpufreq_target()
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A D | loongson1-cpufreq.c | 67 clk_set_parent(policy->clk, cpufreq->osc_clk); in ls1x_cpufreq_target() 73 clk_set_parent(policy->clk, cpufreq->mux_clk); in ls1x_cpufreq_target()
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/linux/sound/soc/samsung/ |
A D | smdk_spdif.c | 55 clk_set_parent(mout_epll, fout_epll); in set_audio_clock_heirachy() 56 clk_set_parent(sclk_audio0, mout_epll); in set_audio_clock_heirachy() 57 clk_set_parent(sclk_spdif, sclk_audio0); in set_audio_clock_heirachy()
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/linux/arch/m68k/coldfire/ |
A D | clk.c | 130 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function 135 EXPORT_SYMBOL(clk_set_parent);
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/linux/drivers/clk/ti/ |
A D | clk-33xx.c | 305 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init() 308 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init() 318 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
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/linux/drivers/clk/mmp/ |
A D | clk-mmp2.c | 249 clk_set_parent(clk, vctcxo); in mmp2_clk_init() 260 clk_set_parent(clk, vctcxo); in mmp2_clk_init() 271 clk_set_parent(clk, vctcxo); in mmp2_clk_init() 282 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
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A D | clk-pxa910.c | 209 clk_set_parent(clk, uart_pll); in pxa910_clk_init() 220 clk_set_parent(clk, uart_pll); in pxa910_clk_init() 231 clk_set_parent(clk, uart_pll); in pxa910_clk_init()
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A D | clk-pxa168.c | 204 clk_set_parent(clk, uart_pll); in pxa168_clk_init() 215 clk_set_parent(clk, uart_pll); in pxa168_clk_init() 226 clk_set_parent(clk, uart_pll); in pxa168_clk_init()
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/linux/drivers/devfreq/ |
A D | imx8m-ddrc.c | 193 ret = clk_set_parent(priv->dram_core, new_dram_core_parent); in imx8m_ddrc_set_freq() 197 ret = clk_set_parent(priv->dram_alt, new_dram_alt_parent); in imx8m_ddrc_set_freq() 203 ret = clk_set_parent(priv->dram_apb, new_dram_apb_parent); in imx8m_ddrc_set_freq()
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/linux/drivers/gpu/drm/imx/ |
A D | imx-ldb.c | 186 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); in imx_ldb_set_clock() 208 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); in imx_ldb_encoder_enable() 209 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); in imx_ldb_encoder_enable() 214 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); in imx_ldb_encoder_enable() 353 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); in imx_ldb_encoder_disable()
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