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Searched refs:config_base (Results 1 – 25 of 57) sorted by relevance

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/linux/arch/arm/kernel/
A Dperf_event_v7.c1073 unsigned long config_base = 0; in armv7pmu_set_event_filter() local
1078 config_base |= ARMV7_EXCLUDE_USER; in armv7pmu_set_event_filter()
1080 config_base |= ARMV7_EXCLUDE_PL1; in armv7pmu_set_event_filter()
1082 config_base |= ARMV7_INCLUDE_HYP; in armv7pmu_set_event_filter()
1088 event->config_base = config_base; in armv7pmu_set_event_filter()
1510 if (hwc->config_base & KRAIT_EVENT_MASK) in krait_pmu_disable_event()
1511 krait_clearpmu(hwc->config_base); in krait_pmu_disable_event()
1541 if (hwc->config_base & KRAIT_EVENT_MASK) in krait_pmu_enable_event()
1587 if (hwc->config_base & VENUM_EVENT) in krait_event_to_bit()
1844 scorpion_clearpmu(hwc->config_base); in scorpion_pmu_disable_event()
[all …]
A Dperf_event_xscale.c219 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | in xscale1pmu_enable_event()
224 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | in xscale1pmu_enable_event()
279 if (XSCALE_PERFCTR_CCNT == hwc->config_base) { in xscale1pmu_get_event_idx()
568 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT; in xscale2pmu_enable_event()
573 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT; in xscale2pmu_enable_event()
578 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT; in xscale2pmu_enable_event()
583 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT; in xscale2pmu_enable_event()
A Dperf_event_v6.c282 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) | in armv6pmu_enable_event()
286 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) | in armv6pmu_enable_event()
393 if (ARMV6_PERFCTR_CPU_CYCLES == hwc->config_base) { in armv6pmu_get_event_idx()
/linux/arch/arm/mach-bcm/
A Dbcm63xx_smp.c37 unsigned long config_base; in scu_a9_enable() local
47 config_base = scu_a9_get_base(); in scu_a9_enable()
48 if (!config_base) { in scu_a9_enable()
53 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
56 config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
A Dplatsmp.c49 unsigned long config_base; in scu_a9_enable() local
58 config_base = scu_a9_get_base(); in scu_a9_enable()
59 if (!config_base) { in scu_a9_enable()
64 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
67 config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_pmu.c219 hwc->config_base = AMDGPU_PMU_PERF_TYPE_NONE; in amdgpu_perf_event_init()
239 switch (hwc->config_base) { in amdgpu_perf_start()
274 switch (hwc->config_base) { in amdgpu_perf_read()
300 switch (hwc->config_base) { in amdgpu_perf_stop()
331 hwc->config_base = AMDGPU_PMU_EVENT_CONFIG_TYPE_DF; in amdgpu_perf_add()
334 hwc->config_base = (hwc->config >> in amdgpu_perf_add()
342 switch (hwc->config_base) { in amdgpu_perf_add()
377 switch (hwc->config_base) { in amdgpu_perf_del()
/linux/drivers/pci/controller/dwc/
A Dpcie-tegra194-acpi.c17 void __iomem *config_base; member
31 pcie_ecam->config_base = cfg->win; in tegra194_acpi_init()
98 return pcie_ecam->config_base + where; in tegra194_map_bus()
/linux/arch/arm64/kernel/
A Dperf_event.c617 armv8pmu_write_evtype(idx - 1, hwc->config_base); in armv8pmu_write_event_type()
621 write_sysreg(hwc->config_base, pmccfiltr_el0); in armv8pmu_write_event_type()
623 armv8pmu_write_evtype(idx, hwc->config_base); in armv8pmu_write_event_type()
909 unsigned long config_base = 0; in armv8pmu_set_event_filter() local
922 config_base |= ARMV8_PMU_INCLUDE_EL2; in armv8pmu_set_event_filter()
924 config_base |= ARMV8_PMU_EXCLUDE_EL1; in armv8pmu_set_event_filter()
926 config_base |= ARMV8_PMU_EXCLUDE_EL0; in armv8pmu_set_event_filter()
929 config_base |= ARMV8_PMU_INCLUDE_EL2; in armv8pmu_set_event_filter()
936 config_base |= ARMV8_PMU_EXCLUDE_EL1; in armv8pmu_set_event_filter()
939 config_base |= ARMV8_PMU_EXCLUDE_EL0; in armv8pmu_set_event_filter()
[all …]
/linux/arch/x86/events/zhaoxin/
A Dcore.c296 rdmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
298 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
305 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in zhaoxin_pmu_disable_event()
332 rdmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
335 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
342 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in zhaoxin_pmu_enable_event()
/linux/arch/s390/kernel/
A Dperf_cpum_cf.c335 if (!(hwc->config_base & cpuhw->info.auth_ctl)) in validate_ctr_auth()
500 hwc->config_base = cpumf_ctr_ctl[set]; in __hw_perf_event_init()
598 ctr_set_enable(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
599 ctr_set_start(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
609 hwc->config_base, true); in cpumf_pmu_start()
616 if ((hwc->config_base & cpumf_ctr_ctl[i])) in cpumf_pmu_start()
673 if (!(hwc->config_base & cpumf_ctr_ctl[i])) in cpumf_pmu_stop()
686 event->hw.config_base, in cpumf_pmu_stop()
1332 event->hw.config_base = get_authctrsets(); in cfdiag_event_init2()
1335 if (!event->hw.config_base) in cfdiag_event_init2()
[all …]
/linux/arch/x86/events/amd/
A Dibs.c304 hwc->config_base = perf_ibs->msr; in perf_ibs_init()
362 rdmsrl(event->hw.config_base, *config); in perf_ibs_event_update()
373 wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask); in perf_ibs_enable_event()
375 wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask); in perf_ibs_enable_event()
390 wrmsrl(hwc->config_base, config); in perf_ibs_disable_event()
392 wrmsrl(hwc->config_base, config); in perf_ibs_disable_event()
448 rdmsrl(hwc->config_base, config); in perf_ibs_stop()
616 msr = hwc->config_base; in perf_ibs_handle_irq()
/linux/drivers/perf/
A Dthunderx2_pmu.c332 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
347 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
362 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_ccpi2()
378 reg_writel(val, hwc->config_base); in uncore_start_event_l3c()
385 reg_writel(0, event->hw.config_base); in uncore_stop_event_l3c()
405 val = reg_readl(hwc->config_base); in uncore_start_event_dmc()
408 reg_writel(val, hwc->config_base); in uncore_start_event_dmc()
425 val = reg_readl(hwc->config_base); in uncore_stop_event_dmc()
427 reg_writel(val, hwc->config_base); in uncore_stop_event_dmc()
445 GET_EVENTID(event, emask)), hwc->config_base); in uncore_start_event_ccpi2()
A Dqcom_l2_pmu.c347 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) { in l2_cache_get_event_idx()
364 group = L2_EVT_GROUP(hwc->config_base); in l2_cache_get_event_idx()
381 if (hwc->config_base != L2CYCLE_CTR_RAW_CODE) in l2_cache_clear_event_idx()
382 clear_bit(L2_EVT_GROUP(hwc->config_base), cluster->used_groups); in l2_cache_clear_event_idx()
530 hwc->config_base = event->attr.config; in l2_cache_event_init()
555 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) { in l2_cache_event_start()
558 config = hwc->config_base; in l2_cache_event_start()
A Darm-ccn.c682 hw->config_base = bit; in arm_ccn_pmu_event_alloc()
703 clear_bit(hw->config_base, source->xp.dt_cmp_mask); in arm_ccn_pmu_event_release()
705 clear_bit(hw->config_base, source->pmu_events_mask); in arm_ccn_pmu_event_release()
949 unsigned long wp = hw->config_base; in arm_ccn_pmu_xp_watchpoint_config()
999 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); in arm_ccn_pmu_xp_event_config()
1007 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); in arm_ccn_pmu_xp_event_config()
1008 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); in arm_ccn_pmu_xp_event_config()
1023 hw->config_base); in arm_ccn_pmu_node_event_config()
1043 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); in arm_ccn_pmu_node_event_config()
1045 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); in arm_ccn_pmu_node_event_config()
/linux/arch/nds32/kernel/
A Dperf_event_cpu.c310 unsigned long config_base = 0; in nds32_pmu_set_event_filter() local
324 config_base |= no_user_tracing; in nds32_pmu_set_event_filter()
327 config_base |= no_kernel_tracing; in nds32_pmu_set_event_filter()
333 event->config_base |= config_base; in nds32_pmu_set_event_filter()
445 hwc->config_base = 0; in nds32_pmu_enable_event()
448 evnum = hwc->config_base; in nds32_pmu_enable_event()
567 unsigned long evtype = hwc->config_base & SOFTWARE_EVENT_MASK; in nds32_pmu_get_event_idx()
817 hwc->config_base = 0; in __hw_perf_event_init()
835 hwc->config_base |= (unsigned long)mapping; in __hw_perf_event_init()
/linux/arch/x86/events/intel/
A Duncore_discovery.c360 wrmsrl(hwc->config_base, hwc->config); in intel_generic_uncore_msr_enable_event()
368 wrmsrl(hwc->config_base, 0); in intel_generic_uncore_msr_disable_event()
411 pci_write_config_dword(pdev, hwc->config_base, hwc->config); in intel_generic_uncore_pci_enable_event()
420 pci_write_config_dword(pdev, hwc->config_base, 0); in intel_generic_uncore_pci_disable_event()
505 writel(hwc->config, box->io_addr + hwc->config_base); in intel_generic_uncore_mmio_enable_event()
516 writel(0, box->io_addr + hwc->config_base); in intel_generic_uncore_mmio_disable_event()
A Duncore_nhmex.c242 wrmsrl(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event()
250 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
252 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
254 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
387 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | in nhmex_bbox_msr_enable_event()
474 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_sbox_msr_enable_event()
862 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_mbox_msr_enable_event()
1147 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | in nhmex_rbox_msr_enable_event()
A Dp6.c164 (void)wrmsrl_safe(hwc->config_base, val); in p6_pmu_disable_event()
181 (void)wrmsrl_safe(hwc->config_base, val); in p6_pmu_enable_event()
A Dknc.c185 (void)wrmsrl_safe(hwc->config_base + hwc->idx, val); in knc_pmu_disable_event()
196 (void)wrmsrl_safe(hwc->config_base + hwc->idx, val); in knc_pmu_enable_event()
A Duncore_snbep.c643 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in snbep_uncore_msr_enable_event()
651 wrmsrl(hwc->config_base, hwc->config); in snbep_uncore_msr_disable_event()
2281 pci_write_config_dword(pdev, hwc->config_base, in knl_uncore_imc_enable_event()
2284 pci_write_config_dword(pdev, hwc->config_base, in knl_uncore_imc_enable_event()
4916 if (!uncore_mmio_is_valid_offset(box, hwc->config_base)) in snr_uncore_mmio_enable_event()
4920 box->io_addr + hwc->config_base); in snr_uncore_mmio_enable_event()
4931 if (!uncore_mmio_is_valid_offset(box, hwc->config_base)) in snr_uncore_mmio_disable_event()
4934 writel(hwc->config, box->io_addr + hwc->config_base); in snr_uncore_mmio_disable_event()
5581 wrmsrl(hwc->config_base, hwc->config); in spr_uncore_msr_enable_event()
5593 wrmsrl(hwc->config_base, 0); in spr_uncore_msr_disable_event()
[all …]
/linux/arch/powerpc/perf/
A Dcore-fsl-emb.c327 write_pmlca(i, event->hw.config_base); in fsl_emb_pmu_add()
536 event->hw.config_base = PMLCA_CE | PMLCA_FCM1 | in fsl_emb_pmu_event_init()
540 event->hw.config_base |= PMLCA_FCU; in fsl_emb_pmu_event_init()
542 event->hw.config_base |= PMLCA_FCS; in fsl_emb_pmu_event_init()
/linux/drivers/pci/controller/
A Dpci-v3-semi.c241 void __iomem *config_base; member
380 return v3->config_base + address + offset; in v3_map_bus()
760 v3->config_base = devm_ioremap_resource(dev, regs); in v3_pci_probe()
761 if (IS_ERR(v3->config_base)) in v3_pci_probe()
762 return PTR_ERR(v3->config_base); in v3_pci_probe()
/linux/arch/alpha/kernel/
A Dperf_event.c200 event[0]->hw.config_base = config; in ev67_check_constraints()
203 event[1]->hw.config_base = config; in ev67_check_constraints()
424 cpuc->config = cpuc->event[0]->hw.config_base; in maybe_change_configuration()
663 hwc->config_base = 0; in __hw_perf_event_init()
/linux/arch/mips/kernel/
A Dperf_event_mipsxx.c358 (evt->config_base & M_PERFCTL_CONFIG_MASK) | in mipsxx_pmu_enable_event()
363 (evt->config_base & M_PERFCTL_CONFIG_MASK) | in mipsxx_pmu_enable_event()
1504 hwc->config_base = MIPS_PERFCTRL_IE; in __hw_perf_event_init()
1511 hwc->config_base |= MIPS_PERFCTRL_U; in __hw_perf_event_init()
1513 hwc->config_base |= MIPS_PERFCTRL_K; in __hw_perf_event_init()
1515 hwc->config_base |= MIPS_PERFCTRL_EXL; in __hw_perf_event_init()
1518 hwc->config_base |= MIPS_PERFCTRL_S; in __hw_perf_event_init()
1520 hwc->config_base &= M_PERFCTL_CONFIG_MASK; in __hw_perf_event_init()
/linux/arch/s390/include/asm/
A Dperf_event.h72 #define SAMPL_FLAGS(hwc) ((hwc)->config_base)

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