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Searched refs:divf (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/clk/
A Dclk-highbank.c97 unsigned long divf, divq, vco_freq, reg; in clk_pll_recalc_rate() local
105 vco_freq = parent_rate * (divf + 1); in clk_pll_recalc_rate()
113 u32 divq, divf; in clk_pll_calc() local
127 divf = (vco_freq + (ref_freq / 2)) / ref_freq; in clk_pll_calc()
128 divf--; in clk_pll_calc()
131 *pdivf = divf; in clk_pll_calc()
137 u32 divq, divf; in clk_pll_round_rate() local
140 clk_pll_calc(rate, ref_freq, &divq, &divf); in clk_pll_round_rate()
142 return (ref_freq * (divf + 1)) / (1 << divq); in clk_pll_round_rate()
149 u32 divq, divf; in clk_pll_set_rate() local
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/linux/drivers/clk/socfpga/
A Dclk-pll-a10.c38 unsigned long divf, divq, reg; in clk_pll_recalc_rate() local
43 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()
45 vco_freq = (unsigned long long)parent_rate * (divf + 1); in clk_pll_recalc_rate()
A Dclk-pll.c42 unsigned long divf, divq, reg; in clk_pll_recalc_rate() local
51 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()
53 vco_freq = (unsigned long long)parent_rate * (divf + 1); in clk_pll_recalc_rate()
/linux/drivers/clk/analogbits/
A Dwrpll-cln28hpc.c303 c->divf = best_f - 1; in wrpll_configure_for_rate()
346 n = parent_rate * fbdiv * (c->divf + 1); in wrpll_calc_output_rate()
/linux/drivers/media/pci/solo6x10/
A Dsolo6x10-core.c524 u32 divq, divf; in solo_pci_probe() local
530 divf = (solo_dev->clock_mhz * 4) / 3 - 1; in solo_pci_probe()
533 divf = (solo_dev->clock_mhz * 2) / 3 - 1; in solo_pci_probe()
540 (divf << 4) | in solo_pci_probe()
/linux/include/linux/clk/
A Danalogbits-wrpll-cln28hpc.h63 u16 divf; member
/linux/drivers/clk/sifive/
A Dsifive-prci.c73 c->divf = v; in __prci_wrpll_unpack()
110 r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; in __prci_wrpll_pack()

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