| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | dpp.h | 163 struct dpp *dpp,
168 struct dpp *dpp,
173 struct dpp *dpp,
177 struct dpp *dpp,
181 struct dpp *dpp,
185 struct dpp *dpp,
189 struct dpp *dpp,
194 struct dpp *dpp,
198 struct dpp *dpp,
202 struct dpp *dpp,
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_dpp_cm.c | 43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
92 struct dcn10_dpp *dpp, in program_gamut_remap() argument
129 dpp->base.ctx, in program_gamut_remap()
139 dpp->base.ctx, in program_gamut_remap()
149 dpp->base.ctx, in program_gamut_remap()
161 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap()
231 dpp->base.ctx, in dpp1_cm_program_color_matrix()
240 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default()
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| A D | dcn10_dpp.c | 42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
133 struct dpp *dpp, in dpp1_get_optimal_number_of_taps() argument
202 dpp->filter_h = NULL; in dpp_reset()
203 dpp->filter_v = NULL; in dpp_reset()
205 memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); in dpp_reset()
206 memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data)); in dpp_reset()
245 dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe; in dpp1_cm_set_regamma_pwl()
268 struct dpp *dpp_base, in dpp1_set_degamma_format_float()
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| A D | dcn10_dpp_dscl.c | 43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
89 struct dcn10_dpp *dpp, in dpp1_dscl_set_overscan() argument
168 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode()
202 struct dpp *dpp_base, in dpp1_power_on_dscl()
224 struct dcn10_dpp *dpp, in dpp1_dscl_set_lb() argument
286 struct dcn10_dpp *dpp, in dpp1_dscl_set_scaler_filter() argument
324 struct dcn10_dpp *dpp, in dpp1_dscl_set_scl_filter() argument
555 struct dpp *dpp_base, in dpp1_dscl_set_scaler_auto_scale()
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| A D | dcn10_hw_sequencer.c | 294 struct dpp *dpp = pool->dpps[i]; in dcn10_log_hw_state() local
297 dpp->funcs->dpp_read_state(dpp, &s); in dcn10_log_hw_state()
1183 struct dpp *dpp, in dcn10_plane_atomic_power_down() argument
1199 dpp->funcs->dpp_reset(dpp); in dcn10_plane_atomic_power_down()
1214 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_plane_atomic_disable() local
1336 dpp->funcs->dpp_reset(dpp); in dcn10_init_pipes()
1342 pipe_ctx->plane_res.dpp = dpp; in dcn10_init_pipes()
1786 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_set_output_transfer_func() local
2488 dpp->funcs->dpp_setup(dpp, in dcn10_update_dpp()
2612 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_update_dchubp_dpp() local
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| A D | dcn10_resource.c | 635 static void dcn10_dpp_destroy(struct dpp **dpp) in dcn10_dpp_destroy() argument
637 kfree(TO_DCN10_DPP(*dpp)); in dcn10_dpp_destroy()
638 *dpp = NULL; in dcn10_dpp_destroy()
645 struct dcn10_dpp *dpp = in dcn10_dpp_create() local
648 if (!dpp) in dcn10_dpp_create()
651 dpp1_construct(dpp, ctx, inst, in dcn10_dpp_create()
653 return &dpp->base; in dcn10_dpp_create()
1431 dc->caps.color.dpp.dcn_arch = 1; in dcn10_resource_construct()
1433 dc->caps.color.dpp.icsc = 1; in dcn10_resource_construct()
1434 dc->caps.color.dpp.dgam_ram = 1; in dcn10_resource_construct()
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| A D | dcn10_dpp.h | 30 #define TO_DCN10_DPP(dpp)\ argument
1353 struct dpp base;
1378 struct dpp *dpp_base,
1382 struct dpp *dpp_base,
1404 struct dpp *dpp_base,
1408 struct dpp *dpp_base,
1412 struct dpp *dpp_base,
1460 struct dpp *dpp_base,
1485 struct dpp *dpp,
1489 struct dpp *dpp_base,
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dpp_cm.c | 34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 struct dpp *dpp_base) in dpp3_enable_cm_block()
84 struct dpp *dpp_base, in dpp3_program_gammcor_lut()
133 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut()
152 struct dpp *dpp_base, in dpp3_program_cm_dealpha()
163 struct dpp *dpp_base, in dpp3_program_cm_bias()
175 struct dcn3_dpp *dpp, in dpp3_gamcor_reg_field() argument
358 dpp->base.ctx, in program_gamut_remap()
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| A D | dcn30_dpp.c | 34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
56 struct dpp *dpp_base, in dpp3_program_post_csc()
119 dpp->base.ctx, in dpp3_program_post_csc()
172 struct dpp *dpp_base, in dpp3_cnv_setup()
377 struct dpp *dpp, in dpp3_get_optimal_number_of_taps() argument
492 struct dpp *dpp_base) in dpp3_deferred_update()
540 struct dpp *dpp_base, in dpp3_power_on_blnd_lut()
560 struct dpp *dpp_base, in dpp3_power_on_hdr3dlut()
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| A D | dcn30_dpp.h | 30 #define TO_DCN30_DPP(dpp)\ argument
31 container_of(dpp, struct dcn3_dpp, base)
559 struct dpp base;
588 struct dpp *dpp_base,
592 struct dpp *dpp_base,
596 struct dpp *dpp_base,
600 struct dpp *dpp_base,
607 struct dpp *dpp_base,
611 struct dpp *dpp_base,
617 struct dpp *dpp_base,
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dpp_cm.c | 37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 struct dpp *dpp_base) in dpp2_enable_cm_block()
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse()
86 struct dpp *dpp_base, in dpp2_program_degamma_lut()
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl()
135 struct dpp *dpp_base, in dpp2_set_degamma()
203 dpp->base.ctx, in program_gamut_remap()
214 struct dpp *dpp_base, in dpp2_cm_set_gamut_remap()
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| A D | dcn20_dpp.c | 42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
76 struct dpp *dpp_base, in dpp2_power_on_obuf()
91 struct dpp *dpp_base, in dpp2_dummy_program_input_lut()
96 struct dpp *dpp_base, in dpp2_cnv_setup()
255 struct dpp *dpp_base, in dpp2_cnv_set_bias_scale()
326 struct dpp *dpp_base, in dpp2_cnv_set_alpha_keyer()
349 struct dpp *dpp_base, in dpp2_set_cursor_attributes()
378 struct dpp *dpp, in oppn20_dummy_program_regamma_pwl() argument
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| A D | dcn20_dpp.h | 30 #define TO_DCN20_DPP(dpp)\ argument
679 struct dpp base;
713 struct dpp *dpp_base,
717 struct dpp *dpp_base,
721 struct dpp *dpp_base,
725 struct dpp *dpp_base,
734 struct dpp *dpp_base,
738 struct dpp *dpp_base,
752 struct dpp *dpp_base,
760 struct dpp *dpp,
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| A D | dcn20_hwseq.c | 574 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_plane_atomic_disable() local
588 dpp->funcs->dpp_dppclk_control(dpp, false, false); in dcn20_plane_atomic_disable()
838 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_blend_lut()
860 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_shaper_3dlut()
891 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_input_transfer_func()
1409 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_update_dchubp_dpp() local
1448 dpp->funcs->dpp_setup(dpp, in dcn20_update_dchubp_dpp()
2524 struct dpp *dpp = res_pool->dpps[i]; in dcn20_fpga_init_hw() local
2526 dpp->funcs->dpp_reset(dpp); in dcn20_fpga_init_hw()
2544 struct dpp *dpp = dc->res_pool->dpps[i]; in dcn20_fpga_init_hw() local
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_dpp.c | 35 dpp->tf_regs->reg
38 dpp->base.ctx
42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
45 struct dpp *dpp_base, in dpp201_cnv_setup()
181 struct dpp *dpp, in dpp201_get_optimal_number_of_taps() argument
290 struct dcn201_dpp *dpp, in dpp201_construct() argument
297 dpp->base.ctx = ctx; in dpp201_construct()
299 dpp->base.inst = inst; in dpp201_construct()
303 dpp->tf_regs = tf_regs; in dpp201_construct()
304 dpp->tf_shift = tf_shift; in dpp201_construct()
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| A D | dcn201_resource.c | 620 static void dcn201_dpp_destroy(struct dpp **dpp) in dcn201_dpp_destroy() argument
622 kfree(TO_DCN201_DPP(*dpp)); in dcn201_dpp_destroy()
623 *dpp = NULL; in dcn201_dpp_destroy()
630 struct dcn201_dpp *dpp = in dcn201_dpp_create() local
633 if (!dpp) in dcn201_dpp_create()
638 return &dpp->base; in dcn201_dpp_create()
640 kfree(dpp); in dcn201_dpp_create()
1113 dc->caps.color.dpp.dcn_arch = 1; in dcn201_resource_construct()
1115 dc->caps.color.dpp.icsc = 1; in dcn201_resource_construct()
1116 dc->caps.color.dpp.dgam_ram = 1; in dcn201_resource_construct()
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| A D | dcn201_dpp.h | 30 #define TO_DCN201_DPP(dpp)\ argument
31 container_of(dpp, struct dcn201_dpp, base)
58 struct dpp base;
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| A D | dcn201_hwseq.c | 298 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
300 dpp->funcs->dpp_reset(dpp); in dcn201_init_hw()
318 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
324 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
325 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
326 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
393 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
579 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( in dcn201_set_cursor_attribute()
580 pipe_ctx->plane_res.dpp, attributes); in dcn201_set_cursor_attribute()
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| /linux/Documentation/devicetree/bindings/media/i2c/ |
| A D | adv7604.yaml | 36 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
37 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
38 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
39 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
40 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
41 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
42 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
43 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
44 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
45 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 720 void dcn301_dpp_destroy(struct dpp **dpp) in dcn301_dpp_destroy() argument
722 kfree(TO_DCN20_DPP(*dpp)); in dcn301_dpp_destroy()
723 *dpp = NULL; in dcn301_dpp_destroy()
726 struct dpp *dcn301_dpp_create( in dcn301_dpp_create()
730 struct dcn3_dpp *dpp = in dcn301_dpp_create() local
733 if (!dpp) in dcn301_dpp_create()
738 return &dpp->base; in dcn301_dpp_create()
741 kfree(dpp); in dcn301_dpp_create()
1457 dc->caps.color.dpp.dcn_arch = 1; in dcn301_resource_construct()
1459 dc->caps.color.dpp.icsc = 1; in dcn301_resource_construct()
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| /linux/arch/sparc/vdso/ |
| A D | vma.c | 250 struct page *dp, **dpp = NULL; in init_vdso_image() local
290 dpp = kcalloc(dnpages, sizeof(struct page *), GFP_KERNEL); in init_vdso_image()
291 vvar_mapping.pages = dpp; in init_vdso_image()
293 if (!dpp) in init_vdso_image()
300 dpp[0] = dp; in init_vdso_image()
318 if (dpp != NULL) { in init_vdso_image()
320 if (dpp[i] != NULL) in init_vdso_image()
321 __free_page(dpp[i]); in init_vdso_image()
323 kfree(dpp); in init_vdso_image()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
| A D | dcn302_resource.c | 676 if (!dpp) in dcn302_dpp_create()
680 return &dpp->base; in dcn302_dpp_create()
683 kfree(dpp); in dcn302_dpp_create()
1527 dc->caps.color.dpp.dcn_arch = 1; in dcn302_resource_construct()
1528 dc->caps.color.dpp.input_lut_shared = 0; in dcn302_resource_construct()
1529 dc->caps.color.dpp.icsc = 1; in dcn302_resource_construct()
1536 dc->caps.color.dpp.post_csc = 1; in dcn302_resource_construct()
1537 dc->caps.color.dpp.gamma_corr = 1; in dcn302_resource_construct()
1540 dc->caps.color.dpp.hw_3d_lut = 1; in dcn302_resource_construct()
1541 dc->caps.color.dpp.ogam_ram = 1; in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
| A D | dcn303_resource.c | 635 if (!dpp) in dcn303_dpp_create()
639 return &dpp->base; in dcn303_dpp_create()
642 kfree(dpp); in dcn303_dpp_create()
1470 dc->caps.color.dpp.dcn_arch = 1; in dcn303_resource_construct()
1471 dc->caps.color.dpp.input_lut_shared = 0; in dcn303_resource_construct()
1472 dc->caps.color.dpp.icsc = 1; in dcn303_resource_construct()
1479 dc->caps.color.dpp.post_csc = 1; in dcn303_resource_construct()
1480 dc->caps.color.dpp.gamma_corr = 1; in dcn303_resource_construct()
1483 dc->caps.color.dpp.hw_3d_lut = 1; in dcn303_resource_construct()
1484 dc->caps.color.dpp.ogam_ram = 1; in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 734 struct dcn20_dpp *dpp = in dcn21_dpp_create() local
737 if (!dpp) in dcn21_dpp_create()
740 if (dpp2_construct(dpp, ctx, inst, in dcn21_dpp_create()
742 return &dpp->base; in dcn21_dpp_create()
745 kfree(dpp); in dcn21_dpp_create()
1997 dc->caps.color.dpp.dcn_arch = 1; in dcn21_resource_construct()
1999 dc->caps.color.dpp.icsc = 1; in dcn21_resource_construct()
2000 dc->caps.color.dpp.dgam_ram = 1; in dcn21_resource_construct()
2006 dc->caps.color.dpp.post_csc = 0; in dcn21_resource_construct()
2011 dc->caps.color.dpp.ogam_ram = 1; in dcn21_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 1054 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
1056 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
1057 *dpp = NULL; in dcn31_dpp_destroy()
1064 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
1067 if (!dpp) in dcn31_dpp_create()
1072 return &dpp->base; in dcn31_dpp_create()
1075 kfree(dpp); in dcn31_dpp_create()
2215 dc->caps.color.dpp.dcn_arch = 1; in dcn31_resource_construct()
2217 dc->caps.color.dpp.icsc = 1; in dcn31_resource_construct()
2224 dc->caps.color.dpp.post_csc = 1; in dcn31_resource_construct()
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