Searched refs:dppclk (Results 1 – 8 of 8) sorted by relevance
143 uint32_t dppclk; member
1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1300 …>display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1312 …ine_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1423 …=dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixe… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1426 …=dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixe… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1643 …v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispcl… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1654 …v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispc… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1655 …v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_de… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1656 …_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sle… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1786 …pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()[all …]
496 input->clks_cfg.dppclk_mhz = v->dppclk; in dcn_bw_calc_rq_dlg_ttu()
346 uint32_t dppclk : 1; member
436 float dppclk; member
252 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; in vg_dump_clk_registers()
1270 new_pipe->update_flags.bits.dppclk = 1; in dcn20_detect_pipe_changes()1337 new_pipe->update_flags.bits.dppclk = 1; in dcn20_detect_pipe_changes()1413 if (pipe_ctx->update_flags.bits.dppclk) in dcn20_update_dchubp_dpp()
322 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; in rn_dump_clk_registers()
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