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Searched refs:dprefclk_khz (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
A Ddcn201_clk_mgr.c237 clk_mgr->base.dprefclk_khz = 600000; in dcn201_clk_mgr_construct()
240 clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT); in dcn201_clk_mgr_construct()
241 clk_mgr->base.dprefclk_khz *= 100; in dcn201_clk_mgr_construct()
243 if (clk_mgr->base.dprefclk_khz == 0) in dcn201_clk_mgr_construct()
244 clk_mgr->base.dprefclk_khz = 600000; in dcn201_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
A Ddce120_clk_mgr.c136 clk_mgr->base.dprefclk_khz = 600000; in dce120_clk_mgr_construct()
143 clk_mgr->base.dprefclk_khz = 625000; in dce121_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Ddcn301_smu.c145 DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000); in dcn301_smu_set_dprefclk()
150 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn301_smu_set_dprefclk()
A Dvg_clk_mgr.c379 s->dprefclk_khz = sb.dprefclk * 1000; in vg_get_clk_states()
802 clk_mgr->base.base.dprefclk_khz = 600000; in vg_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h221 uint32_t dprefclk_khz; member
277 …int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where th… member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_smu.c160 return clk_mgr->base.dprefclk_khz; in dcn31_smu_set_dprefclk()
165 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn31_smu_set_dprefclk()
A Ddcn31_clk_mgr.c698 clk_mgr->base.base.dprefclk_khz = 600000; in dcn31_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
A Drv1_clk_mgr_vbios_smu.c153 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rv1_vbios_smu_set_dprefclk()
A Drv1_clk_mgr.c334 clk_mgr->base.dprefclk_khz = 600000; in rv1_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr_vbios_smu.c153 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rn_vbios_smu_set_dprefclk()
A Drn_clk_mgr.c448 s->dprefclk_khz = sb.dprefclk * 1000; in rn_get_clk_states()
1008 clk_mgr->base.dprefclk_khz = 600000; in rn_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clk_mgr.c178 return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz); in dce12_get_dp_ref_freq_khz()
932 clk_mgr_dce->dprefclk_khz = 600000; in dce120_clk_mgr_create()
953 clk_mgr_dce->dprefclk_khz = 625000; in dce121_clk_mgr_create()
A Ddce_clock_source.c1017 clock_source->ctx->dc->clk_mgr->dprefclk_khz*10, in get_pixel_clk_frequency_100hz()
1101 clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000); in dcn20_program_pix_clk()
1137 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; in dcn3_program_pix_clk()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c550 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved in dcn20_clk_mgr_construct()
585 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn20_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c549 clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved in dcn3_clk_mgr_construct()
570 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000; in dcn3_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
A Ddce_clk_mgr.c159 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz); in dce12_get_dp_ref_freq_khz()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hw_sequencer.c2070 dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10; in dcn10_align_pixel_clocks()

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