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Searched refs:dram_clock_change_latency_us (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c204 .dram_clock_change_latency_us = 23.84,
224 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
232 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
244 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; in calculate_wm_set_for_vlevel()
321 dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in dcn301_fpu_init_soc_bounding_box()
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_socbb.h71 uint32_t dram_clock_change_latency_us; member
/linux/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_structs.h112 double dram_clock_change_latency_us; member
A Ddml1_display_rq_dlg_calc.c1308 mode_lib->soc.dram_clock_change_latency_us in dml1_rq_dlg_get_dlg_params()
1324 (double) mode_lib->soc.dram_clock_change_latency_us); in dml1_rq_dlg_get_dlg_params()
A Ddisplay_mode_vba.c242 mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us; in fetch_socbb_params()
243 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; in fetch_socbb_params()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c212 .dram_clock_change_latency_us = 404,
1743 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in init_soc_bounding_box()
2152 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_calculate_wm_and_dlg_fp()
2206 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[… in dcn30_calculate_wm_and_dlg_fp()
2272 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_calculate_wm_and_dlg_fp()
2279 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_update_soc_for_wm_a()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c300 .dram_clock_change_latency_us = 23.84,
1042 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
1050 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
1062 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; in calculate_wm_set_for_vlevel()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c334 .dram_clock_change_latency_us = 404.0,
445 .dram_clock_change_latency_us = 404.0,
3262 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; in dcn20_validate_bandwidth_fp()
3286 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn20_validate_bandwidth_fp()
3300 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; in dcn20_validate_bandwidth_fp()
3620 if ((int)(bb->dram_clock_change_latency_us * 1000) in dcn20_patch_bounding_box()
3623 bb->dram_clock_change_latency_us = in dcn20_patch_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c1848 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
1888 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()
1910 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()
1929 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_build_wm_range_table()
/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c195 .dram_clock_change_latency_us = 404,
1116 dcn3_02_soc.dram_clock_change_latency_us = in init_soc_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c177 .dram_clock_change_latency_us = 404,
1042 dcn3_03_soc.dram_clock_change_latency_us = in init_soc_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_resource.c228 .dram_clock_change_latency_us = 250.0,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_rq_dlg_calc_20.c1093 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20_rq_dlg_get_dlg_params()
A Ddisplay_rq_dlg_calc_20v2.c1094 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20v2_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_resource.c130 .dram_clock_change_latency_us = 17.0,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_rq_dlg_calc_21.c1141 mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_rq_dlg_calc_30.c1333 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/calcs/
A Ddcn_calcs.c1768 dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency; in dcn_bw_sync_calcs_and_dml()

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