Searched refs:dram_clock_change_latency_us (Results 1 – 19 of 19) sorted by relevance
204 .dram_clock_change_latency_us = 23.84,224 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()232 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()244 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; in calculate_wm_set_for_vlevel()321 dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in dcn301_fpu_init_soc_bounding_box()
71 uint32_t dram_clock_change_latency_us; member
112 double dram_clock_change_latency_us; member
1308 mode_lib->soc.dram_clock_change_latency_us in dml1_rq_dlg_get_dlg_params()1324 (double) mode_lib->soc.dram_clock_change_latency_us); in dml1_rq_dlg_get_dlg_params()
242 mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us; in fetch_socbb_params()243 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; in fetch_socbb_params()
212 .dram_clock_change_latency_us = 404,1743 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in init_soc_bounding_box()2152 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_calculate_wm_and_dlg_fp()2206 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[… in dcn30_calculate_wm_and_dlg_fp()2272 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_calculate_wm_and_dlg_fp()2279 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_update_soc_for_wm_a()
300 .dram_clock_change_latency_us = 23.84,1042 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()1050 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()1062 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; in calculate_wm_set_for_vlevel()
334 .dram_clock_change_latency_us = 404.0,445 .dram_clock_change_latency_us = 404.0,3262 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; in dcn20_validate_bandwidth_fp()3286 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn20_validate_bandwidth_fp()3300 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; in dcn20_validate_bandwidth_fp()3620 if ((int)(bb->dram_clock_change_latency_us * 1000) in dcn20_patch_bounding_box()3623 bb->dram_clock_change_latency_us = in dcn20_patch_bounding_box()
1848 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()1888 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()1910 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()1929 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()
110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_build_wm_range_table()
195 .dram_clock_change_latency_us = 404,1116 dcn3_02_soc.dram_clock_change_latency_us = in init_soc_bounding_box()
177 .dram_clock_change_latency_us = 404,1042 dcn3_03_soc.dram_clock_change_latency_us = in init_soc_bounding_box()
228 .dram_clock_change_latency_us = 250.0,
1093 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20_rq_dlg_get_dlg_params()
1094 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20v2_rq_dlg_get_dlg_params()
130 .dram_clock_change_latency_us = 17.0,
1141 mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
1333 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
1768 dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency; in dcn_bw_sync_calcs_and_dml()
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