Searched refs:ih_rb_base (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | vega10_ih.c | 53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega10_ih_init_register_offset()
66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega10_ih_init_register_offset()
77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in vega10_ih_init_register_offset()
217 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in vega10_ih_enable_ring()
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| A D | vega20_ih.c | 56 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega20_ih_init_register_offset()
69 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega20_ih_init_register_offset()
80 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in vega20_ih_init_register_offset()
221 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in vega20_ih_enable_ring()
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| A D | navi10_ih.c | 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in navi10_ih_init_register_offset()
68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in navi10_ih_init_register_offset()
79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in navi10_ih_init_register_offset()
272 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in navi10_ih_enable_ring()
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| A D | amdgpu_ih.h | 34 uint32_t ih_rb_base; member
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