Searched refs:indexing (Results 1 – 25 of 40) sorted by relevance
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294 synth->indexing.currindex++; in synth_insert_next_index()296 if (synth->indexing.currindex > in synth_insert_next_index()297 synth->indexing.highindex) in synth_insert_next_index()298 synth->indexing.currindex = in synth_insert_next_index()299 synth->indexing.lowindex; in synth_insert_next_index()302 out = synth->indexing.currindex * 10 + sent_num; in synth_insert_next_index()303 synth_printf(synth->indexing.command, out, out); in synth_insert_next_index()314 if ((ind / 10) <= synth->indexing.currindex) in spk_get_index_count()317 index_count = synth->indexing.currindex in spk_get_index_count()318 - synth->indexing.lowindex in spk_get_index_count()[all …]
100 .indexing = {
101 .indexing = {
106 .indexing = {
104 .indexing = {
113 .indexing = {
108 .indexing = {
115 .indexing = {
201 struct synth_indexing indexing; member
132 .indexing = {
109 .indexing = {
118 .indexing = {
141 .indexing = {
133 .indexing = {
139 .indexing = {
110 interrupts, specified in order of their indexing by the SMMU.139 input IDs). This property is not valid for SMMUs using stream indexing, or187 /* SMMU with stream matching or stream indexing */
9 a btree for indexing and the layout is optimized for SSDs.
60 enum cache_indexing indexing; member
392 tcache->cache_attrs.indexing = NODE_CACHE_DIRECT_MAP; in hmat_parse_cache()395 tcache->cache_attrs.indexing = NODE_CACHE_INDEXED; in hmat_parse_cache()399 tcache->cache_attrs.indexing = NODE_CACHE_OTHER; in hmat_parse_cache()
133 * The GPIO controller base in the global pin indexing space is pin135 * in the global pin indexing space.
153 What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/indexing157 The caches associativity indexing: 0 for direct mapped,
21 The number of bits in the key segment used for indexing into the25 The position (in the key) of the key segment used for indexing into
23 into the register, instead indexing begins at 1. The optional property
157 | |-- indexing162 The "indexing" will be 0 if it is a direct-mapped cache, and non-zero
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