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Searched refs:ixLCAC_MC1_OVR_SEL (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
A Dsmu_6_0_d.h30 #define ixLCAC_MC1_OVR_SEL 0x0120 macro
A Dsmu_8_0_d.h636 #define ixLCAC_MC1_OVR_SEL 0xd0208140 macro
A Dsmu_7_0_0_d.h729 #define ixLCAC_MC1_OVR_SEL 0xc0400d40 macro
A Dsmu_7_1_1_d.h1029 #define ixLCAC_MC1_OVR_SEL 0xc0400140 macro
A Dsmu_7_0_1_d.h1219 #define ixLCAC_MC1_OVR_SEL 0xc0400d40 macro
A Dsmu_7_1_2_d.h1180 #define ixLCAC_MC1_OVR_SEL 0xc0400140 macro
A Dsmu_7_1_3_d.h1112 #define ixLCAC_MC1_OVR_SEL 0xc0400140 macro
A Dsmu_7_1_0_d.h1248 #define ixLCAC_MC1_OVR_SEL 0xc0400d40 macro
/linux/drivers/gpu/drm/amd/pm/powerplay/
A Dkv_dpm.c542 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);

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