/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
A D | dcn30_hubp.c | 126 address->grph.meta_addr.low_part); in hubp3_program_surface_flip_and_addr() 135 address->grph.addr.low_part); in hubp3_program_surface_flip_and_addr() 180 address->video_progressive.luma_addr.low_part); in hubp3_program_surface_flip_and_addr() 232 address->grph_stereo.left_meta_addr.low_part); in hubp3_program_surface_flip_and_addr() 249 address->grph_stereo.right_addr.low_part); in hubp3_program_surface_flip_and_addr() 257 address->grph_stereo.left_alpha_addr.low_part); in hubp3_program_surface_flip_and_addr() 265 address->grph_stereo.left_addr.low_part); in hubp3_program_surface_flip_and_addr() 286 address->rgbea.alpha_meta_addr.low_part); in hubp3_program_surface_flip_and_addr() 294 address->rgbea.meta_addr.low_part); in hubp3_program_surface_flip_and_addr() 303 address->rgbea.alpha_addr.low_part); in hubp3_program_surface_flip_and_addr() [all …]
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A D | dcn30_mmhubbub.c | 84 …SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_part); in mmhubbub3_warmup_mcif()
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/linux/drivers/gpu/drm/amd/display/dmub/src/ |
A D | dmub_dcn30.c | 102 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load() 111 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load() 136 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows() 151 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows() 162 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows() 169 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows() 179 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows() 186 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows() 195 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
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A D | dmub_dcn20.c | 169 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn20_backdoor_load() 178 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn20_backdoor_load() 205 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); in dmub_dcn20_setup_windows() 220 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); in dmub_dcn20_setup_windows() 232 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); in dmub_dcn20_setup_windows() 239 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); in dmub_dcn20_setup_windows() 249 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); in dmub_dcn20_setup_windows() 256 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); in dmub_dcn20_setup_windows() 265 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); in dmub_dcn20_setup_windows()
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A D | dmub_dcn31.c | 156 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn31_backdoor_load() 165 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn31_backdoor_load() 187 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); in dmub_dcn31_setup_windows() 196 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); in dmub_dcn31_setup_windows() 205 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); in dmub_dcn31_setup_windows() 212 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); in dmub_dcn31_setup_windows() 221 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); in dmub_dcn31_setup_windows()
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/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
A D | dcn10_hubp.c | 402 address->grph.meta_addr.low_part); in hubp1_program_surface_flip_and_addr() 411 address->grph.addr.low_part); in hubp1_program_surface_flip_and_addr() 431 address->video_progressive.chroma_meta_addr.low_part); in hubp1_program_surface_flip_and_addr() 439 address->video_progressive.luma_meta_addr.low_part); in hubp1_program_surface_flip_and_addr() 448 address->video_progressive.chroma_addr.low_part); in hubp1_program_surface_flip_and_addr() 456 address->video_progressive.luma_addr.low_part); in hubp1_program_surface_flip_and_addr() 482 address->grph_stereo.right_meta_addr.low_part); in hubp1_program_surface_flip_and_addr() 492 address->grph_stereo.left_meta_addr.low_part); in hubp1_program_surface_flip_and_addr() 501 address->grph_stereo.right_addr.low_part); in hubp1_program_surface_flip_and_addr() 509 address->grph_stereo.left_addr.low_part); in hubp1_program_surface_flip_and_addr() [all …]
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A D | dcn10_hw_sequencer.c | 2286 PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part); in mmhub_read_vm_system_aperture_settings() 2315 PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part); in mmhub_read_vm_context0_settings() 2320 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part); in mmhub_read_vm_context0_settings() 2325 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part); in mmhub_read_vm_context0_settings() 2330 PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part); in mmhub_read_vm_context0_settings()
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/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
A D | dcn21_hubp.c | 718 address->grph.meta_addr.low_part; in hubp21_program_surface_flip_and_addr() 724 address->grph.addr.low_part; in hubp21_program_surface_flip_and_addr() 735 address->video_progressive.luma_meta_addr.low_part; in hubp21_program_surface_flip_and_addr() 740 address->video_progressive.chroma_meta_addr.low_part; in hubp21_program_surface_flip_and_addr() 746 address->video_progressive.luma_addr.low_part; in hubp21_program_surface_flip_and_addr() 751 address->video_progressive.chroma_addr.low_part; in hubp21_program_surface_flip_and_addr() 767 address->grph_stereo.right_meta_addr.low_part; in hubp21_program_surface_flip_and_addr() 774 address->grph_stereo.left_meta_addr.low_part; in hubp21_program_surface_flip_and_addr() 780 address->grph_stereo.left_addr.low_part; in hubp21_program_surface_flip_and_addr() 785 address->grph_stereo.right_addr.low_part; in hubp21_program_surface_flip_and_addr()
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/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
A D | dcn20_hubp.c | 604 CURSOR_SURFACE_ADDRESS, attr->address.low_part); in hubp2_cursor_set_attributes() 646 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part); in hubp2_dmdata_set_attributes() 751 address->grph.meta_addr.low_part); in hubp2_program_surface_flip_and_addr() 760 address->grph.addr.low_part); in hubp2_program_surface_flip_and_addr() 788 address->video_progressive.luma_meta_addr.low_part); in hubp2_program_surface_flip_and_addr() 797 address->video_progressive.chroma_addr.low_part); in hubp2_program_surface_flip_and_addr() 805 address->video_progressive.luma_addr.low_part); in hubp2_program_surface_flip_and_addr() 831 address->grph_stereo.right_meta_addr.low_part); in hubp2_program_surface_flip_and_addr() 841 address->grph_stereo.left_meta_addr.low_part); in hubp2_program_surface_flip_and_addr() 850 address->grph_stereo.right_addr.low_part); in hubp2_program_surface_flip_and_addr() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/inc/ |
A D | compressor.h | 42 uint32_t low_part; member
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/linux/drivers/gpu/drm/amd/amdkfd/ |
A D | kfd_dbgdev.h | 182 uint32_t low_part; member
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A D | kfd_dbgdev.c | 93 ib_packet->bitfields2.ib_base_lo = largep->u.low_part >> 2; in dbgdev_diq_submit_ib() 140 rm_packet->bitfields4.address_lo_32b = addr.u.low_part >> 2; in dbgdev_diq_submit_ib() 255 (addr.u.low_part >> ADDRESS_WATCH_REG_ADDLOW_SHIFT); in dbgdev_address_watch_set_registers()
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/linux/drivers/gpu/drm/amd/display/dc/ |
A D | dc_hw_types.h | 47 uint32_t low_part; member 52 uint32_t low_part; member
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/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
A D | dcn201_hwseq.c | 209 hws->fb_base.low_part = fb_base; in read_mmhub_vm_setup() 212 hws->fb_top.low_part = fb_top; in read_mmhub_vm_setup() 214 hws->fb_offset.low_part = fb_offset; in read_mmhub_vm_setup()
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/linux/drivers/gpu/drm/amd/display/dc/dce/ |
A D | dce_ipp.c | 133 CURSOR_SURFACE_ADDRESS, attributes->address.low_part); in dce_ipp_cursor_set_attributes()
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A D | dce_mem_input.c | 806 GRPH_SECONDARY_SURFACE_ADDRESS, address.low_part >> 8, in program_sec_addr() 821 address.low_part >> 8); in program_pri_addr()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
A D | dcn31_clk_mgr.c | 484 clk_mgr_dcn31->smu_wm_set.mc_address.low_part); in dcn31_notify_wm_ranges() 504 smu_dpm_clks->mc_address.low_part); in dcn31_get_dpm_table_from_smu()
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/linux/drivers/gpu/drm/amd/display/dc/dce110/ |
A D | dce110_mem_input_v.c | 81 temp = address.low_part >> in program_pri_addr_c() 117 temp = address.low_part >> in program_pri_addr_l()
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A D | dce110_compressor.c | 305 compressor->compr_surface_address.addr.low_part; in dce110_compressor_program_compressed_surface_address_and_pitch()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
A D | vg_clk_mgr.c | 473 clk_mgr_vgh->smu_wm_set.mc_address.low_part); in vg_notify_wm_ranges() 725 smu_dpm_clks->mc_address.low_part); in vg_get_dpm_table_from_smu()
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/linux/drivers/gpu/drm/amd/display/dc/dce60/ |
A D | dce60_hw_sequencer.c | 352 pipe_ctx->plane_state->address.grph.addr.low_part, in dce60_program_front_end_for_pipe()
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/linux/drivers/gpu/drm/amd/display/dc/dce112/ |
A D | dce112_compressor.c | 490 compressor->compr_surface_address.addr.low_part; in dce112_compressor_program_compressed_surface_address_and_pitch()
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/linux/fs/ntfs/ |
A D | layout.h | 1294 u32 low_part; /* Low 32-bits. */ member
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/linux/drivers/gpu/drm/amd/display/dmub/inc/ |
A D | dmub_cmd.h | 187 uint32_t low_part; /**< Lower 32 bits */ member
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
A D | amdgpu_dm.c | 1192 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); in mmhub_read_system_context() 1194 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); in mmhub_read_system_context() 1196 page_table_base.low_part = lower_32_bits(pt_base); in mmhub_read_system_context() 5249 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); in fill_gfx9_plane_attributes_from_modifiers() 5294 address->grph.addr.low_part = lower_32_bits(addr); in fill_plane_buffer_attributes() 5317 address->video_progressive.luma_addr.low_part = in fill_plane_buffer_attributes() 5321 address->video_progressive.chroma_addr.low_part = in fill_plane_buffer_attributes() 8753 attributes.address.low_part = lower_32_bits(address); in handle_cursor_update() 9131 bundle->flip_addrs[planes_count].address.grph.addr.low_part); in amdgpu_dm_commit_planes()
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