Home
last modified time | relevance | path

Searched refs:mmUVD_CGC_CTRL (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Duvd_v5_0.c679 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
718 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating()
773 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
776 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
782 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
785 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
850 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_get_clockgating_state()
A Duvd_v3_1.c213 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_set_dcm()
229 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v3_1_set_dcm()
607 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
610 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
616 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
619 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
A Duvd_v4_2.c614 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
617 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
623 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
626 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
637 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_set_dcm()
653 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v4_2_set_dcm()
A Duvd_v6_0.c1336 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1376 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_set_sw_clock_gating()
1433 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1436 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1442 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1445 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1515 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_get_clockgating_state()
A Dvcn_v1_0.c461 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
469 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
494 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
515 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
585 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
592 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
594 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
615 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
673 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
A Dvcn_v2_5.c547 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
554 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
582 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
603 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
681 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
712 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
719 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
721 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
741 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
A Dvcn_v2_0.c488 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
495 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
520 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
541 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
618 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
648 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
655 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
657 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
678 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
A Dvcn_v3_0.c685 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
692 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
720 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
741 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
841 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
869 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
876 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
878 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
899 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
A Duvd_v7_0.c861 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), in uvd_v7_0_sriov_start()
974 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start()
1611 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1657 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
A Duvd_4_0_d.h34 #define mmUVD_CGC_CTRL 0x3D2C macro
A Duvd_4_2_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
A Duvd_3_1_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
A Duvd_5_0_d.h50 #define mmUVD_CGC_CTRL 0x3d2c macro
A Duvd_6_0_d.h66 #define mmUVD_CGC_CTRL 0x3d2c macro
A Duvd_7_0_offset.h146 #define mmUVD_CGC_CTRL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
A Dvcn_1_0_offset.h308 #define mmUVD_CGC_CTRL … macro
A Dvcn_2_5_offset.h501 #define mmUVD_CGC_CTRL … macro
A Dvcn_2_0_0_offset.h508 #define mmUVD_CGC_CTRL … macro
A Dvcn_3_0_0_offset.h817 #define mmUVD_CGC_CTRL … macro

Completed in 56 milliseconds