Searched refs:mmUVD_MPC_SET_MUXA0 (Results 1 – 19 of 19) sorted by relevance
| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| A D | uvd_4_0_d.h | 56 #define mmUVD_MPC_SET_MUXA0 0x3D79 macro
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| A D | uvd_4_2_d.h | 54 #define mmUVD_MPC_SET_MUXA0 0x3d79 macro
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| A D | uvd_3_1_d.h | 56 #define mmUVD_MPC_SET_MUXA0 0x3d79 macro
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| A D | uvd_5_0_d.h | 60 #define mmUVD_MPC_SET_MUXA0 0x3d79 macro
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| A D | uvd_6_0_d.h | 76 #define mmUVD_MPC_SET_MUXA0 0x3d79 macro
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| A D | uvd_7_0_offset.h | 166 #define mmUVD_MPC_SET_MUXA0 … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| A D | vcn_1_0_offset.h | 346 #define mmUVD_MPC_SET_MUXA0 … macro
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| A D | vcn_2_5_offset.h | 761 #define mmUVD_MPC_SET_MUXA0 … macro
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| A D | vcn_2_0_0_offset.h | 596 #define mmUVD_MPC_SET_MUXA0 … macro
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| A D | vcn_3_0_0_offset.h | 1141 #define mmUVD_MPC_SET_MUXA0 … macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | uvd_v3_1.c | 361 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v3_1_start()
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| A D | uvd_v4_2.c | 317 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v4_2_start()
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| A D | uvd_v5_0.c | 363 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v5_0_start()
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| A D | vcn_v1_0.c | 819 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, in vcn_v1_0_start_spg_mode()
1002 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0, in vcn_v1_0_start_dpg_mode()
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| A D | vcn_v2_5.c | 807 VCN, 0, mmUVD_MPC_SET_MUXA0), in vcn_v2_5_start_dpg_mode()
961 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, in vcn_v2_5_start()
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| A D | vcn_v2_0.c | 833 UVD, 0, mmUVD_MPC_SET_MUXA0), in vcn_v2_0_start_dpg_mode()
968 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, in vcn_v2_0_start()
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| A D | vcn_v3_0.c | 973 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), in vcn_v3_0_start_dpg_mode()
1139 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, in vcn_v3_0_start()
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| A D | uvd_v6_0.c | 777 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v6_0_start()
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| A D | uvd_v7_0.c | 1016 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v7_0_start()
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