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Searched refs:mmUVD_MPC_SET_MUXA1 (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
A Duvd_4_0_d.h57 #define mmUVD_MPC_SET_MUXA1 0x3D7A macro
A Duvd_4_2_d.h55 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
A Duvd_3_1_d.h57 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
A Duvd_5_0_d.h61 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
A Duvd_6_0_d.h77 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
A Duvd_7_0_offset.h168 #define mmUVD_MPC_SET_MUXA1 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
A Dvcn_1_0_offset.h348 #define mmUVD_MPC_SET_MUXA1 macro
A Dvcn_2_5_offset.h763 #define mmUVD_MPC_SET_MUXA1 macro
A Dvcn_2_0_0_offset.h598 #define mmUVD_MPC_SET_MUXA1 macro
A Dvcn_3_0_0_offset.h1143 #define mmUVD_MPC_SET_MUXA1 macro
/linux/drivers/gpu/drm/amd/amdgpu/
A Duvd_v3_1.c362 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v3_1_start()
A Duvd_v4_2.c318 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v4_2_start()
A Duvd_v5_0.c364 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v5_0_start()
A Duvd_v6_0.c778 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v6_0_start()
A Duvd_v7_0.c1017 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v7_0_start()

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