| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| A D | uvd_4_0_d.h | 73 #define mmUVD_RBC_RB_WPTR 0x3DA5 macro
|
| A D | uvd_4_2_d.h | 72 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
|
| A D | uvd_3_1_d.h | 74 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
|
| A D | uvd_5_0_d.h | 78 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
|
| A D | uvd_6_0_d.h | 94 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
|
| A D | uvd_7_0_offset.h | 200 #define mmUVD_RBC_RB_WPTR … macro
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | uvd_v3_1.c | 62 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v3_1_ring_get_wptr()
76 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v3_1_ring_set_wptr()
427 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v3_1_start()
|
| A D | uvd_v4_2.c | 76 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v4_2_ring_get_wptr()
90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_ring_set_wptr()
385 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_start()
|
| A D | uvd_v5_0.c | 74 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v5_0_ring_get_wptr()
88 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_ring_set_wptr()
442 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_start()
|
| A D | vcn_v1_0.c | 927 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_start_spg_mode()
1085 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_start_dpg_mode()
1179 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v1_0_stop_dpg_mode()
1255 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_pause_dpg_mode()
1316 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_pause_dpg_mode()
1394 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); in vcn_v1_0_dec_ring_get_wptr()
1412 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_dec_ring_set_wptr()
|
| A D | vcn_v2_0.c | 912 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_start_dpg_mode()
1070 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_start()
1110 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v2_0_stop_dpg_mode()
1246 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_pause_dpg_mode()
1335 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); in vcn_v2_0_dec_ring_get_wptr()
1357 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_dec_ring_set_wptr()
|
| A D | vcn_v2_5.c | 891 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start_dpg_mode()
1069 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start()
1306 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v2_5_stop_dpg_mode()
1490 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v2_5_dec_ring_get_wptr()
1508 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_dec_ring_set_wptr()
|
| A D | vcn_v3_0.c | 1061 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start_dpg_mode()
1237 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start()
1490 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v3_0_stop_dpg_mode()
1637 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); in vcn_v3_0_pause_dpg_mode()
1686 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v3_0_dec_ring_get_wptr()
1713 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_dec_ring_set_wptr()
|
| A D | uvd_v6_0.c | 111 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v6_0_ring_get_wptr()
142 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_ring_set_wptr()
857 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
|
| A D | uvd_v7_0.c | 105 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); in uvd_v7_0_ring_get_wptr()
139 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
1104 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, in uvd_v7_0_start()
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| A D | vcn_1_0_offset.h | 386 #define mmUVD_RBC_RB_WPTR … macro
|
| A D | vcn_2_5_offset.h | 791 #define mmUVD_RBC_RB_WPTR … macro
|
| A D | vcn_2_0_0_offset.h | 682 #define mmUVD_RBC_RB_WPTR … macro
|
| A D | vcn_3_0_0_offset.h | 1175 #define mmUVD_RBC_RB_WPTR … macro
|