| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| A D | uvd_4_0_d.h | 88 #define mmUVD_VCPU_CACHE_OFFSET0 0x3D36 macro
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| A D | uvd_4_2_d.h | 60 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
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| A D | uvd_3_1_d.h | 62 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
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| A D | uvd_5_0_d.h | 66 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
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| A D | uvd_6_0_d.h | 82 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
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| A D | uvd_7_0_offset.h | 178 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | vcn_v2_5.c | 395 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
403 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_5_mc_resume()
450 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
457 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
469 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_mc_resume_dpg_mode()
1194 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); in vcn_v2_5_sriov_start()
1206 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_sriov_start()
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| A D | vcn_v2_0.c | 335 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_0_mc_resume()
343 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_0_mc_resume()
392 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
399 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
411 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_0_mc_resume_dpg_mode()
1901 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_0_start_sriov()
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| A D | vcn_v3_0.c | 441 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
449 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v3_0_mc_resume()
495 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
502 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
514 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_mc_resume_dpg_mode()
1327 mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_start_sriov()
1338 mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_start_sriov()
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| A D | uvd_v7_0.c | 685 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in uvd_v7_0_mc_resume()
693 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, in uvd_v7_0_mc_resume()
827 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); in uvd_v7_0_sriov_start()
835 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in uvd_v7_0_sriov_start()
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| A D | vcn_v1_0.c | 305 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v1_0_mc_resume_spg_mode()
313 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume_spg_mode()
374 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, in vcn_v1_0_mc_resume_dpg_mode()
383 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume_dpg_mode()
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| A D | uvd_v3_1.c | 248 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); in uvd_v3_1_mc_resume()
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| A D | uvd_v4_2.c | 577 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); in uvd_v4_2_mc_resume()
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| A D | uvd_v5_0.c | 289 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v5_0_mc_resume()
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| A D | uvd_v6_0.c | 613 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v6_0_mc_resume()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| A D | vcn_1_0_offset.h | 364 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
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| A D | vcn_2_5_offset.h | 685 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
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| A D | vcn_2_0_0_offset.h | 614 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
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| A D | vcn_3_0_0_offset.h | 1061 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
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